Commit 5add5ebc authored by Claudiu Beznea's avatar Claudiu Beznea Committed by Geert Uytterhoeven
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clk: renesas: r9a08g045: Add support for power domains 



Instantiate power domains for the currently enabled IPs of the R9A08G045
SoC.

Signed-off-by: default avatarClaudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
Link: https://lore.kernel.org/r/20240422105355.1622177-8-claudiu.beznea.uj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 0c8a59b3

drivers/clk/renesas/r9a08g045-cpg.c

+41 −0
Original line number Diff line number Diff line
@@ -240,6 +240,43 @@ static const unsigned int r9a08g045_crit_mod_clks[] __initconst = { 
	MOD_CLK_BASE + R9A08G045_DMAC_ACLK,

};



static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = {

	/* Keep always-on domain on the first position for proper domains registration. */

	DEF_PD("always-on",	R9A08G045_PD_ALWAYS_ON,

				DEF_REG_CONF(0, 0),

				RZG2L_PD_F_ALWAYS_ON),

	DEF_PD("gic",		R9A08G045_PD_GIC,

				DEF_REG_CONF(CPG_BUS_ACPU_MSTOP, BIT(3)),

				RZG2L_PD_F_ALWAYS_ON),

	DEF_PD("ia55",		R9A08G045_PD_IA55,

				DEF_REG_CONF(CPG_BUS_PERI_CPU_MSTOP, BIT(13)),

				RZG2L_PD_F_ALWAYS_ON),

	DEF_PD("dmac",		R9A08G045_PD_DMAC,

				DEF_REG_CONF(CPG_BUS_REG1_MSTOP, GENMASK(3, 0)),

				RZG2L_PD_F_ALWAYS_ON),

	DEF_PD("wdt0",		R9A08G045_PD_WDT0,

				DEF_REG_CONF(CPG_BUS_REG0_MSTOP, BIT(0)),

				RZG2L_PD_F_NONE),

	DEF_PD("sdhi0",		R9A08G045_PD_SDHI0,

				DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(0)),

				RZG2L_PD_F_NONE),

	DEF_PD("sdhi1",		R9A08G045_PD_SDHI1,

				DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(1)),

				RZG2L_PD_F_NONE),

	DEF_PD("sdhi2",		R9A08G045_PD_SDHI2,

				DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(11)),

				RZG2L_PD_F_NONE),

	DEF_PD("eth0",		R9A08G045_PD_ETHER0,

				DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(2)),

				RZG2L_PD_F_NONE),

	DEF_PD("eth1",		R9A08G045_PD_ETHER1,

				DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(3)),

				RZG2L_PD_F_NONE),

	DEF_PD("scif0",		R9A08G045_PD_SCIF0,

				DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(1)),

				RZG2L_PD_F_NONE),

};



const struct rzg2l_cpg_info r9a08g045_cpg_info = {

	/* Core Clocks */

	.core_clks = r9a08g045_core_clks,
@@ -260,5 +297,9 @@ const struct rzg2l_cpg_info r9a08g045_cpg_info = { 
	.resets = r9a08g045_resets,

	.num_resets = R9A08G045_VBAT_BRESETN + 1, /* Last reset ID + 1 */



	/* Power domains */

	.pm_domains = r9a08g045_pm_domains,

	.num_pm_domains = ARRAY_SIZE(r9a08g045_pm_domains),



	.has_clk_mon_regs = true,

};