Commit 5c163c97 authored by Rob Herring (Arm)'s avatar Rob Herring (Arm) Committed by Bartosz Golaszewski
Browse files

dt-bindings: gpio: Convert cavium,octeon-3860-gpio to DT schema 



Convert the Cavium Octeon 3860 GPIO binding to DT schema format. It's a
straight forward conversion.

Looks like Octeon has no maintainers, so Bartosz is listed.

Signed-off-by: default avatarRob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250714202927.3012974-1-robh@kernel.org


Signed-off-by: default avatarBartosz Golaszewski <bartosz.golaszewski@linaro.org>
parent 98ce0e1c

Documentation/devicetree/bindings/gpio/cavium,octeon-3860-gpio.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/cavium,octeon-3860-gpio.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Cavium Octeon 3860 GPIO controller



maintainers:

  - Bartosz Golaszewski <brgl@bgdev.pl>



properties:

  compatible:

    const: cavium,octeon-3860-gpio



  reg:

    maxItems: 1



  gpio-controller: true



  '#gpio-cells':

    const: 2



  interrupt-controller: true



  '#interrupt-cells':

    const: 2



  interrupts:

    maxItems: 16



required:

  - compatible

  - reg

  - gpio-controller

  - '#gpio-cells'

  - interrupt-controller

  - '#interrupt-cells'

  - interrupts



additionalProperties: false



examples:

  - |

    bus {

        #address-cells = <2>;

        #size-cells = <2>;



        gpio@1070000000800 {

            compatible = "cavium,octeon-3860-gpio";

            reg = <0x10700 0x00000800 0x0 0x100>;

            gpio-controller;

            #gpio-cells = <2>;

            interrupt-controller;

            #interrupt-cells = <2>;

            /* The GPIO pin connect to 16 consecutive CUI bits */

            interrupts = <0 16>, <0 17>, <0 18>, <0 19>,

                        <0 20>, <0 21>, <0 22>, <0 23>,

                        <0 24>, <0 25>, <0 26>, <0 27>,

                        <0 28>, <0 29>, <0 30>, <0 31>;

        };

    };

Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt

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* General Purpose Input Output (GPIO) bus.



Properties:

- compatible: "cavium,octeon-3860-gpio"



  Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.



- reg: The base address of the GPIO unit's register bank.



- gpio-controller: This is a GPIO controller.



- #gpio-cells: Must be <2>.  The first cell is the GPIO pin.



- interrupt-controller: The GPIO controller is also an interrupt

  controller, many of its pins may be configured as an interrupt

  source.



- #interrupt-cells: Must be <2>.  The first cell is the GPIO pin

   connected to the interrupt source.  The second cell is the interrupt

   triggering protocol and may have one of four values:

   1 - edge triggered on the rising edge.

   2 - edge triggered on the falling edge

   4 - level triggered active high.

   8 - level triggered active low.



- interrupts: Interrupt routing for each pin.



Example:



	gpio-controller@1070000000800 {

		#gpio-cells = <2>;

		compatible = "cavium,octeon-3860-gpio";

		reg = <0x10700 0x00000800 0x0 0x100>;

		gpio-controller;

		/* Interrupts are specified by two parts:

		 * 1) GPIO pin number (0..15)

		 * 2) Triggering (1 - edge rising

		 *		  2 - edge falling

		 *		  4 - level active high

		 *		  8 - level active low)

		 */

		interrupt-controller;

		#interrupt-cells = <2>;

		/* The GPIO pin connect to 16 consecutive CUI bits */

		interrupts = <0 16>, <0 17>, <0 18>, <0 19>,

			     <0 20>, <0 21>, <0 22>, <0 23>,

			     <0 24>, <0 25>, <0 26>, <0 27>,

			     <0 28>, <0 29>, <0 30>, <0 31>;

	};