Commit 5c932d16 authored by Vinod Koul's avatar Vinod Koul
Browse files

Merge tag 'ti-serdes-for-5.13' into next 

TI Serdes changes for 5.13
parents d9de0cbd 4709b21a

Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml

+17 −3
Original line number Diff line number Diff line
@@ -28,13 +28,27 @@ properties: 
  '#size-cells':

    const: 0



  '#clock-cells':

    const: 1



  clocks:

    maxItems: 1

    minItems: 1

    maxItems: 2

    description:

      PHY reference clock. Must contain an entry in clock-names.

      PHY reference clock for 1 item. Must contain an entry in clock-names.

      Optional Parent to enable output reference clock.



  clock-names:

    const: refclk

    minItems: 1

    items:

      - const: refclk

      - const: phy_en_refclk



  assigned-clocks:

    maxItems: 3



  assigned-clock-parents:

    maxItems: 3



  reg:

    minItems: 1

Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml

+4 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ properties: 
    enum:

      - ti,j721e-wiz-16g

      - ti,j721e-wiz-10g

      - ti,am64-wiz-10g



  power-domains:

    maxItems: 1
@@ -42,6 +43,9 @@ properties: 
  "#reset-cells":

    const: 1



  "#clock-cells":

    const: 1



  ranges: true



  assigned-clocks:

include/dt-bindings/mux/ti-serdes.h

+5 −0
Original line number Diff line number Diff line
@@ -90,4 +90,9 @@ 
#define J7200_SERDES0_LANE3_USB			0x2

#define J7200_SERDES0_LANE3_IP4_UNUSED		0x3



/* AM64 */



#define AM64_SERDES0_LANE0_PCIE0		0x0

#define AM64_SERDES0_LANE0_USB			0x1



#endif /* _DT_BINDINGS_MUX_TI_SERDES */

include/dt-bindings/phy/phy-cadence-torrent.h

+2 −0
Original line number Diff line number Diff line
@@ -10,4 +10,6 @@ 
#define TORRENT_SERDES_EXTERNAL_SSC	1

#define TORRENT_SERDES_INTERNAL_SSC	2



#define CDNS_TORRENT_REFCLK_DRIVER      0



#endif /* _DT_BINDINGS_TORRENT_SERDES_H */

include/dt-bindings/phy/phy-ti.h

0 → 100644
+21 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/*

 * This header provides constants for TI SERDES.

 */



#ifndef _DT_BINDINGS_TI_SERDES

#define _DT_BINDINGS_TI_SERDES



/* Clock index for output clocks from WIZ */



/* MUX Clocks */

#define TI_WIZ_PLL0_REFCLK	0

#define TI_WIZ_PLL1_REFCLK	1

#define TI_WIZ_REFCLK_DIG	2



/* Reserve index here for future additions */



/* MISC Clocks */

#define TI_WIZ_PHY_EN_REFCLK	16



#endif /* _DT_BINDINGS_TI_SERDES */