Commit 5d5b4e8c authored by Mark Brown's avatar Mark Brown Committed by Catalin Marinas
Browse files

arm64/sve: Report FEAT_SVE_B16B16 to userspace 



SVE 2.1 introduced a new feature FEAT_SVE_B16B16 which adds instructions
supporting the BFloat16 floating point format. Report this to userspace
through the ID registers and hwcap.

Reported-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20230915-arm64-zfr-b16b16-el0-v1-1-f9aba807bdb5@kernel.org


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 6465e260

Documentation/arch/arm64/cpu-feature-registers.rst

+2 −0
Original line number Diff line number Diff line
@@ -268,6 +268,8 @@ infrastructure: 
     +------------------------------+---------+---------+

     | SHA3                         | [35-32] |    y    |

     +------------------------------+---------+---------+

     | B16B16                       | [27-24] |    y    |

     +------------------------------+---------+---------+

     | BF16                         | [23-20] |    y    |

     +------------------------------+---------+---------+

     | BitPerm                      | [19-16] |    y    |

Documentation/arch/arm64/elf_hwcaps.rst

+3 −0
Original line number Diff line number Diff line
@@ -308,6 +308,9 @@ HWCAP2_MOPS 
HWCAP2_HBC

    Functionality implied by ID_AA64ISAR2_EL1.BC == 0b0001.



HWCAP2_SVE_B16B16

    Functionality implied by ID_AA64ZFR0_EL1.B16B16 == 0b0001.



4. Unused AT_HWCAP bits

-----------------------

arch/arm64/include/asm/hwcap.h

+1 −0
Original line number Diff line number Diff line
@@ -139,6 +139,7 @@ 
#define KERNEL_HWCAP_SME_F16F16		__khwcap2_feature(SME_F16F16)

#define KERNEL_HWCAP_MOPS		__khwcap2_feature(MOPS)

#define KERNEL_HWCAP_HBC		__khwcap2_feature(HBC)

#define KERNEL_HWCAP_SVE_B16B16		__khwcap2_feature(SVE_B16B16)



/*

 * This yields a mask that user programs can use to figure out what

arch/arm64/include/uapi/asm/hwcap.h

+1 −0
Original line number Diff line number Diff line
@@ -104,5 +104,6 @@ 
#define HWCAP2_SME_F16F16	(1UL << 42)

#define HWCAP2_MOPS		(1UL << 43)

#define HWCAP2_HBC		(1UL << 44)

#define HWCAP2_SVE_B16B16	(1UL << 45)



#endif /* _UAPI__ASM_HWCAP_H */

arch/arm64/kernel/cpufeature.c

+3 −0
Original line number Diff line number Diff line
@@ -278,6 +278,8 @@ static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 
		       FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),

		       FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),

		       FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_B16B16_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),

		       FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
@@ -2821,6 +2823,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 
	HWCAP_CAP(ID_AA64ZFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES),

	HWCAP_CAP(ID_AA64ZFR0_EL1, AES, PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),

	HWCAP_CAP(ID_AA64ZFR0_EL1, BitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),

	HWCAP_CAP(ID_AA64ZFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_B16B16),

	HWCAP_CAP(ID_AA64ZFR0_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16),

	HWCAP_CAP(ID_AA64ZFR0_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16),

	HWCAP_CAP(ID_AA64ZFR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),