Commit 5db19c48 authored by Alok Singh's avatar Alok Singh Committed by Jeff Johnson
Browse files

wifi: ath12k: Move MU user processing to Wi-Fi 7 module 



Move Wi-Fi 7-specific monitor functionality out of ath12k common code
into the Wi-Fi 7 module to improve modularity.

Move and rename the following MU user processing functions to
wifi7/dp_mon.c with the ath12k_wifi7_ prefix:
- ath12k_dp_mon_rx_handle_ofdma_info()
- ath12k_dp_mon_rx_populate_mu_user_info()
- ath12k_dp_mon_hal_rx_parse_user_info()

Move the helper functions hal_rx_mon_hal_ru_size_to_ath12k_ru_size and
hal_rx_ul_ofdma_ru_size_to_width to the Wi-Fi 7 module, and export the
helpers required by the ath12k_wifi7 code. Isolate the parsing of
MU-specific user information within the Wi-Fi 7 module to keep
common code generic.

Tested-on: QCN9274 hw2.0 PCI WLAN.WBE.1.5-01651-QCAHKSWPL_SILICONZ-1

Signed-off-by: default avatarAlok Singh <quic_aloksing@quicinc.com>
Reviewed-by: default avatarVasanthakumar Thiagarajan <vasanthakumar.thiagarajan@oss.qualcomm.com>
Reviewed-by: default avatarBaochen Qiang <baochen.qiang@oss.qualcomm.com>
Link: https://patch.msgid.link/20251110103713.3484779-11-quic_aloksing@quicinc.com


Signed-off-by: default avatarJeff Johnson <jeff.johnson@oss.qualcomm.com>
parent e5419861

drivers/net/wireless/ath/ath12k/dp_mon.c

+0 −351
Original line number Diff line number Diff line
@@ -11,357 +11,6 @@ 
#include "dp_tx.h"

#include "peer.h"



void

ath12k_dp_mon_rx_handle_ofdma_info(const struct hal_rx_ppdu_end_user_stats *ppdu_end_user,

				   struct hal_rx_user_status *rx_user_status)

{

	rx_user_status->ul_ofdma_user_v0_word0 =

		__le32_to_cpu(ppdu_end_user->usr_resp_ref);

	rx_user_status->ul_ofdma_user_v0_word1 =

		__le32_to_cpu(ppdu_end_user->usr_resp_ref_ext);

}

EXPORT_SYMBOL(ath12k_dp_mon_rx_handle_ofdma_info);



static void

ath12k_dp_mon_rx_populate_byte_count(const struct hal_rx_ppdu_end_user_stats *stats,

				     void *ppduinfo,

				     struct hal_rx_user_status *rx_user_status)

{

	rx_user_status->mpdu_ok_byte_count =

		le32_get_bits(stats->info7,

			      HAL_RX_PPDU_END_USER_STATS_INFO7_MPDU_OK_BYTE_COUNT);

	rx_user_status->mpdu_err_byte_count =

		le32_get_bits(stats->info8,

			      HAL_RX_PPDU_END_USER_STATS_INFO8_MPDU_ERR_BYTE_COUNT);

}



void

ath12k_dp_mon_rx_populate_mu_user_info(const struct hal_rx_ppdu_end_user_stats *rx_tlv,

				       struct hal_rx_mon_ppdu_info *ppdu_info,

				       struct hal_rx_user_status *rx_user_status)

{

	rx_user_status->ast_index = ppdu_info->ast_index;

	rx_user_status->tid = ppdu_info->tid;

	rx_user_status->tcp_ack_msdu_count =

		ppdu_info->tcp_ack_msdu_count;

	rx_user_status->tcp_msdu_count =

		ppdu_info->tcp_msdu_count;

	rx_user_status->udp_msdu_count =

		ppdu_info->udp_msdu_count;

	rx_user_status->other_msdu_count =

		ppdu_info->other_msdu_count;

	rx_user_status->frame_control = ppdu_info->frame_control;

	rx_user_status->frame_control_info_valid =

		ppdu_info->frame_control_info_valid;

	rx_user_status->data_sequence_control_info_valid =

		ppdu_info->data_sequence_control_info_valid;

	rx_user_status->first_data_seq_ctrl =

		ppdu_info->first_data_seq_ctrl;

	rx_user_status->preamble_type = ppdu_info->preamble_type;

	rx_user_status->ht_flags = ppdu_info->ht_flags;

	rx_user_status->vht_flags = ppdu_info->vht_flags;

	rx_user_status->he_flags = ppdu_info->he_flags;

	rx_user_status->rs_flags = ppdu_info->rs_flags;



	rx_user_status->mpdu_cnt_fcs_ok =

		ppdu_info->num_mpdu_fcs_ok;

	rx_user_status->mpdu_cnt_fcs_err =

		ppdu_info->num_mpdu_fcs_err;

	memcpy(&rx_user_status->mpdu_fcs_ok_bitmap[0], &ppdu_info->mpdu_fcs_ok_bitmap[0],

	       HAL_RX_NUM_WORDS_PER_PPDU_BITMAP *

	       sizeof(ppdu_info->mpdu_fcs_ok_bitmap[0]));



	ath12k_dp_mon_rx_populate_byte_count(rx_tlv, ppdu_info, rx_user_status);

}

EXPORT_SYMBOL(ath12k_dp_mon_rx_populate_mu_user_info);



static inline enum ath12k_eht_ru_size

hal_rx_mon_hal_ru_size_to_ath12k_ru_size(u32 hal_ru_size)

{

	switch (hal_ru_size) {

	case HAL_EHT_RU_26:

		return ATH12K_EHT_RU_26;

	case HAL_EHT_RU_52:

		return ATH12K_EHT_RU_52;

	case HAL_EHT_RU_78:

		return ATH12K_EHT_RU_52_26;

	case HAL_EHT_RU_106:

		return ATH12K_EHT_RU_106;

	case HAL_EHT_RU_132:

		return ATH12K_EHT_RU_106_26;

	case HAL_EHT_RU_242:

		return ATH12K_EHT_RU_242;

	case HAL_EHT_RU_484:

		return ATH12K_EHT_RU_484;

	case HAL_EHT_RU_726:

		return ATH12K_EHT_RU_484_242;

	case HAL_EHT_RU_996:

		return ATH12K_EHT_RU_996;

	case HAL_EHT_RU_996x2:

		return ATH12K_EHT_RU_996x2;

	case HAL_EHT_RU_996x3:

		return ATH12K_EHT_RU_996x3;

	case HAL_EHT_RU_996x4:

		return ATH12K_EHT_RU_996x4;

	case HAL_EHT_RU_NONE:

		return ATH12K_EHT_RU_INVALID;

	case HAL_EHT_RU_996_484:

		return ATH12K_EHT_RU_996_484;

	case HAL_EHT_RU_996x2_484:

		return ATH12K_EHT_RU_996x2_484;

	case HAL_EHT_RU_996x3_484:

		return ATH12K_EHT_RU_996x3_484;

	case HAL_EHT_RU_996_484_242:

		return ATH12K_EHT_RU_996_484_242;

	default:

		return ATH12K_EHT_RU_INVALID;

	}

}



static inline u32

hal_rx_ul_ofdma_ru_size_to_width(enum ath12k_eht_ru_size ru_size)

{

	switch (ru_size) {

	case ATH12K_EHT_RU_26:

		return RU_26;

	case ATH12K_EHT_RU_52:

		return RU_52;

	case ATH12K_EHT_RU_52_26:

		return RU_52_26;

	case ATH12K_EHT_RU_106:

		return RU_106;

	case ATH12K_EHT_RU_106_26:

		return RU_106_26;

	case ATH12K_EHT_RU_242:

		return RU_242;

	case ATH12K_EHT_RU_484:

		return RU_484;

	case ATH12K_EHT_RU_484_242:

		return RU_484_242;

	case ATH12K_EHT_RU_996:

		return RU_996;

	case ATH12K_EHT_RU_996_484:

		return RU_996_484;

	case ATH12K_EHT_RU_996_484_242:

		return RU_996_484_242;

	case ATH12K_EHT_RU_996x2:

		return RU_2X996;

	case ATH12K_EHT_RU_996x2_484:

		return RU_2X996_484;

	case ATH12K_EHT_RU_996x3:

		return RU_3X996;

	case ATH12K_EHT_RU_996x3_484:

		return RU_3X996_484;

	case ATH12K_EHT_RU_996x4:

		return RU_4X996;

	default:

		return RU_INVALID;

	}

}



void

ath12k_dp_mon_hal_rx_parse_user_info(const struct hal_receive_user_info *rx_usr_info,

				     u16 user_id,

				     struct hal_rx_mon_ppdu_info *ppdu_info)

{

	struct hal_rx_user_status *mon_rx_user_status = NULL;

	struct hal_rx_radiotap_eht *eht = &ppdu_info->eht_info.eht;

	enum ath12k_eht_ru_size rtap_ru_size = ATH12K_EHT_RU_INVALID;

	u32 ru_width, reception_type, ru_index = HAL_EHT_RU_INVALID;

	u32 ru_type_80_0, ru_start_index_80_0;

	u32 ru_type_80_1, ru_start_index_80_1;

	u32 ru_type_80_2, ru_start_index_80_2;

	u32 ru_type_80_3, ru_start_index_80_3;

	u32 ru_size = 0, num_80mhz_with_ru = 0;

	u64 ru_index_320mhz = 0;

	u32 ru_index_per80mhz;



	reception_type = le32_get_bits(rx_usr_info->info0,

				       HAL_RX_USR_INFO0_RECEPTION_TYPE);



	switch (reception_type) {

	case HAL_RECEPTION_TYPE_SU:

		ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;

		break;

	case HAL_RECEPTION_TYPE_DL_MU_MIMO:

	case HAL_RECEPTION_TYPE_UL_MU_MIMO:

		ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO;

		break;

	case HAL_RECEPTION_TYPE_DL_MU_OFMA:

	case HAL_RECEPTION_TYPE_UL_MU_OFDMA:

		ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_OFDMA;

		break;

	case HAL_RECEPTION_TYPE_DL_MU_OFDMA_MIMO:

	case HAL_RECEPTION_TYPE_UL_MU_OFDMA_MIMO:

		ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO;

	}



	ppdu_info->is_stbc = le32_get_bits(rx_usr_info->info0, HAL_RX_USR_INFO0_STBC);

	ppdu_info->ldpc = le32_get_bits(rx_usr_info->info2, HAL_RX_USR_INFO2_LDPC);

	ppdu_info->dcm = le32_get_bits(rx_usr_info->info2, HAL_RX_USR_INFO2_STA_DCM);

	ppdu_info->bw = le32_get_bits(rx_usr_info->info1, HAL_RX_USR_INFO1_RX_BW);

	ppdu_info->mcs = le32_get_bits(rx_usr_info->info1, HAL_RX_USR_INFO1_MCS);

	ppdu_info->nss = le32_get_bits(rx_usr_info->info2, HAL_RX_USR_INFO2_NSS) + 1;



	if (user_id < HAL_MAX_UL_MU_USERS) {

		mon_rx_user_status = &ppdu_info->userstats[user_id];

		mon_rx_user_status->mcs = ppdu_info->mcs;

		mon_rx_user_status->nss = ppdu_info->nss;

	}



	if (!(ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_MIMO ||

	      ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_OFDMA ||

	      ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO))

		return;



	/* RU allocation present only for OFDMA reception */

	ru_type_80_0 = le32_get_bits(rx_usr_info->info2, HAL_RX_USR_INFO2_RU_TYPE_80_0);

	ru_start_index_80_0 = le32_get_bits(rx_usr_info->info3,

					    HAL_RX_USR_INFO3_RU_START_IDX_80_0);

	if (ru_type_80_0 != HAL_EHT_RU_NONE) {

		ru_size += ru_type_80_0;

		ru_index_per80mhz = ru_start_index_80_0;

		ru_index = ru_index_per80mhz;

		ru_index_320mhz |= HAL_RU_PER80(ru_type_80_0, 0, ru_index_per80mhz);

		num_80mhz_with_ru++;

	}



	ru_type_80_1 = le32_get_bits(rx_usr_info->info2, HAL_RX_USR_INFO2_RU_TYPE_80_1);

	ru_start_index_80_1 = le32_get_bits(rx_usr_info->info3,

					    HAL_RX_USR_INFO3_RU_START_IDX_80_1);

	if (ru_type_80_1 != HAL_EHT_RU_NONE) {

		ru_size += ru_type_80_1;

		ru_index_per80mhz = ru_start_index_80_1;

		ru_index = ru_index_per80mhz;

		ru_index_320mhz |= HAL_RU_PER80(ru_type_80_1, 1, ru_index_per80mhz);

		num_80mhz_with_ru++;

	}



	ru_type_80_2 = le32_get_bits(rx_usr_info->info2, HAL_RX_USR_INFO2_RU_TYPE_80_2);

	ru_start_index_80_2 = le32_get_bits(rx_usr_info->info3,

					    HAL_RX_USR_INFO3_RU_START_IDX_80_2);

	if (ru_type_80_2 != HAL_EHT_RU_NONE) {

		ru_size += ru_type_80_2;

		ru_index_per80mhz = ru_start_index_80_2;

		ru_index = ru_index_per80mhz;

		ru_index_320mhz |= HAL_RU_PER80(ru_type_80_2, 2, ru_index_per80mhz);

		num_80mhz_with_ru++;

	}



	ru_type_80_3 = le32_get_bits(rx_usr_info->info2, HAL_RX_USR_INFO2_RU_TYPE_80_3);

	ru_start_index_80_3 = le32_get_bits(rx_usr_info->info2,

					    HAL_RX_USR_INFO3_RU_START_IDX_80_3);

	if (ru_type_80_3 != HAL_EHT_RU_NONE) {

		ru_size += ru_type_80_3;

		ru_index_per80mhz = ru_start_index_80_3;

		ru_index = ru_index_per80mhz;

		ru_index_320mhz |= HAL_RU_PER80(ru_type_80_3, 3, ru_index_per80mhz);

		num_80mhz_with_ru++;

	}



	if (num_80mhz_with_ru > 1) {

		/* Calculate the MRU index */

		switch (ru_index_320mhz) {

		case HAL_EHT_RU_996_484_0:

		case HAL_EHT_RU_996x2_484_0:

		case HAL_EHT_RU_996x3_484_0:

			ru_index = 0;

			break;

		case HAL_EHT_RU_996_484_1:

		case HAL_EHT_RU_996x2_484_1:

		case HAL_EHT_RU_996x3_484_1:

			ru_index = 1;

			break;

		case HAL_EHT_RU_996_484_2:

		case HAL_EHT_RU_996x2_484_2:

		case HAL_EHT_RU_996x3_484_2:

			ru_index = 2;

			break;

		case HAL_EHT_RU_996_484_3:

		case HAL_EHT_RU_996x2_484_3:

		case HAL_EHT_RU_996x3_484_3:

			ru_index = 3;

			break;

		case HAL_EHT_RU_996_484_4:

		case HAL_EHT_RU_996x2_484_4:

		case HAL_EHT_RU_996x3_484_4:

			ru_index = 4;

			break;

		case HAL_EHT_RU_996_484_5:

		case HAL_EHT_RU_996x2_484_5:

		case HAL_EHT_RU_996x3_484_5:

			ru_index = 5;

			break;

		case HAL_EHT_RU_996_484_6:

		case HAL_EHT_RU_996x2_484_6:

		case HAL_EHT_RU_996x3_484_6:

			ru_index = 6;

			break;

		case HAL_EHT_RU_996_484_7:

		case HAL_EHT_RU_996x2_484_7:

		case HAL_EHT_RU_996x3_484_7:

			ru_index = 7;

			break;

		case HAL_EHT_RU_996x2_484_8:

			ru_index = 8;

			break;

		case HAL_EHT_RU_996x2_484_9:

			ru_index = 9;

			break;

		case HAL_EHT_RU_996x2_484_10:

			ru_index = 10;

			break;

		case HAL_EHT_RU_996x2_484_11:

			ru_index = 11;

			break;

		default:

			ru_index = HAL_EHT_RU_INVALID;

			break;

		}



		ru_size += 4;

	}



	rtap_ru_size = hal_rx_mon_hal_ru_size_to_ath12k_ru_size(ru_size);

	if (rtap_ru_size != ATH12K_EHT_RU_INVALID) {

		u32 known, data;



		known = __le32_to_cpu(eht->known);

		known |= IEEE80211_RADIOTAP_EHT_KNOWN_RU_MRU_SIZE_OM;

		eht->known = cpu_to_le32(known);



		data = __le32_to_cpu(eht->data[1]);

		data |=	u32_encode_bits(rtap_ru_size,

					IEEE80211_RADIOTAP_EHT_DATA1_RU_SIZE);

		eht->data[1] = cpu_to_le32(data);

	}



	if (ru_index != HAL_EHT_RU_INVALID) {

		u32 known, data;



		known = __le32_to_cpu(eht->known);

		known |= IEEE80211_RADIOTAP_EHT_KNOWN_RU_MRU_INDEX_OM;

		eht->known = cpu_to_le32(known);



		data = __le32_to_cpu(eht->data[1]);

		data |=	u32_encode_bits(rtap_ru_size,

					IEEE80211_RADIOTAP_EHT_DATA1_RU_INDEX);

		eht->data[1] = cpu_to_le32(data);

	}



	if (mon_rx_user_status && ru_index != HAL_EHT_RU_INVALID &&

	    rtap_ru_size != ATH12K_EHT_RU_INVALID) {

		mon_rx_user_status->ul_ofdma_ru_start_index = ru_index;

		mon_rx_user_status->ul_ofdma_ru_size = rtap_ru_size;



		ru_width = hal_rx_ul_ofdma_ru_size_to_width(rtap_ru_size);



		mon_rx_user_status->ul_ofdma_ru_width = ru_width;

		mon_rx_user_status->ofdma_info_valid = 1;

	}

}

EXPORT_SYMBOL(ath12k_dp_mon_hal_rx_parse_user_info);



static void ath12k_dp_mon_parse_rx_msdu_end_err(u32 info, u32 *errmap)

{

	if (info & RX_MSDU_END_INFO13_FCS_ERR)

drivers/net/wireless/ath/ath12k/dp_mon.h

+0 −11
Original line number Diff line number Diff line
@@ -120,17 +120,6 @@ ath12k_dp_mon_parse_status_buf(struct ath12k_pdev_dp *dp_pdev, 
			       struct ath12k_mon_data *pmon,

			       const struct dp_mon_packet_info *packet_info);

void

ath12k_dp_mon_rx_handle_ofdma_info(const struct hal_rx_ppdu_end_user_stats *ppdu_end_user,

				   struct hal_rx_user_status *rx_user_status);

void

ath12k_dp_mon_rx_populate_mu_user_info(const struct hal_rx_ppdu_end_user_stats *rx_tlv,

				       struct hal_rx_mon_ppdu_info *ppdu_info,

				       struct hal_rx_user_status *rx_user_status);

void

ath12k_dp_mon_hal_rx_parse_user_info(const struct hal_receive_user_info *rx_usr_info,

				     u16 user_id,

				     struct hal_rx_mon_ppdu_info *ppdu_info);

void

ath12k_dp_mon_parse_status_msdu_end(struct ath12k_mon_data *pmon,

				    const struct hal_rx_msdu_end *msdu_end);

#endif

drivers/net/wireless/ath/ath12k/wifi7/dp_mon.c

+352 −4
Original line number Diff line number Diff line
@@ -31,6 +31,354 @@ ath12k_wifi7_dp_mon_rx_memset_ppdu_info(struct hal_rx_mon_ppdu_info *ppdu_info) 
	ppdu_info->peer_id = HAL_INVALID_PEERID;

}



static void

ath12k_wifi7_dp_mon_rx_handle_ofdma_info(const struct hal_rx_ppdu_end_user_stats *ppdu_end_user,

					 struct hal_rx_user_status *rx_user_status)

{

	rx_user_status->ul_ofdma_user_v0_word0 =

		__le32_to_cpu(ppdu_end_user->usr_resp_ref);

	rx_user_status->ul_ofdma_user_v0_word1 =

		__le32_to_cpu(ppdu_end_user->usr_resp_ref_ext);

}



static void

ath12k_wifi7_dp_mon_rx_populate_byte_count(const struct hal_rx_ppdu_end_user_stats *stats,

					   void *ppduinfo,

					   struct hal_rx_user_status *rx_user_status)

{

	rx_user_status->mpdu_ok_byte_count =

		le32_get_bits(stats->info7,

			      HAL_RX_PPDU_END_USER_STATS_INFO7_MPDU_OK_BYTE_COUNT);

	rx_user_status->mpdu_err_byte_count =

		le32_get_bits(stats->info8,

			      HAL_RX_PPDU_END_USER_STATS_INFO8_MPDU_ERR_BYTE_COUNT);

}



static void

ath12k_wifi7_dp_mon_rx_populate_mu_user_info(const struct hal_rx_ppdu_end_user_stats *rx_tlv,

					     struct hal_rx_mon_ppdu_info *ppdu_info,

					     struct hal_rx_user_status *rx_user_status)

{

	rx_user_status->ast_index = ppdu_info->ast_index;

	rx_user_status->tid = ppdu_info->tid;

	rx_user_status->tcp_ack_msdu_count =

		ppdu_info->tcp_ack_msdu_count;

	rx_user_status->tcp_msdu_count =

		ppdu_info->tcp_msdu_count;

	rx_user_status->udp_msdu_count =

		ppdu_info->udp_msdu_count;

	rx_user_status->other_msdu_count =

		ppdu_info->other_msdu_count;

	rx_user_status->frame_control = ppdu_info->frame_control;

	rx_user_status->frame_control_info_valid =

		ppdu_info->frame_control_info_valid;

	rx_user_status->data_sequence_control_info_valid =

		ppdu_info->data_sequence_control_info_valid;

	rx_user_status->first_data_seq_ctrl =

		ppdu_info->first_data_seq_ctrl;

	rx_user_status->preamble_type = ppdu_info->preamble_type;

	rx_user_status->ht_flags = ppdu_info->ht_flags;

	rx_user_status->vht_flags = ppdu_info->vht_flags;

	rx_user_status->he_flags = ppdu_info->he_flags;

	rx_user_status->rs_flags = ppdu_info->rs_flags;



	rx_user_status->mpdu_cnt_fcs_ok =

		ppdu_info->num_mpdu_fcs_ok;

	rx_user_status->mpdu_cnt_fcs_err =

		ppdu_info->num_mpdu_fcs_err;

	memcpy(&rx_user_status->mpdu_fcs_ok_bitmap[0], &ppdu_info->mpdu_fcs_ok_bitmap[0],

	       HAL_RX_NUM_WORDS_PER_PPDU_BITMAP *

	       sizeof(ppdu_info->mpdu_fcs_ok_bitmap[0]));



	ath12k_wifi7_dp_mon_rx_populate_byte_count(rx_tlv, ppdu_info, rx_user_status);

}



static inline enum ath12k_eht_ru_size

hal_rx_mon_hal_ru_size_to_ath12k_ru_size(u32 hal_ru_size)

{

	switch (hal_ru_size) {

	case HAL_EHT_RU_26:

		return ATH12K_EHT_RU_26;

	case HAL_EHT_RU_52:

		return ATH12K_EHT_RU_52;

	case HAL_EHT_RU_78:

		return ATH12K_EHT_RU_52_26;

	case HAL_EHT_RU_106:

		return ATH12K_EHT_RU_106;

	case HAL_EHT_RU_132:

		return ATH12K_EHT_RU_106_26;

	case HAL_EHT_RU_242:

		return ATH12K_EHT_RU_242;

	case HAL_EHT_RU_484:

		return ATH12K_EHT_RU_484;

	case HAL_EHT_RU_726:

		return ATH12K_EHT_RU_484_242;

	case HAL_EHT_RU_996:

		return ATH12K_EHT_RU_996;

	case HAL_EHT_RU_996x2:

		return ATH12K_EHT_RU_996x2;

	case HAL_EHT_RU_996x3:

		return ATH12K_EHT_RU_996x3;

	case HAL_EHT_RU_996x4:

		return ATH12K_EHT_RU_996x4;

	case HAL_EHT_RU_NONE:

		return ATH12K_EHT_RU_INVALID;

	case HAL_EHT_RU_996_484:

		return ATH12K_EHT_RU_996_484;

	case HAL_EHT_RU_996x2_484:

		return ATH12K_EHT_RU_996x2_484;

	case HAL_EHT_RU_996x3_484:

		return ATH12K_EHT_RU_996x3_484;

	case HAL_EHT_RU_996_484_242:

		return ATH12K_EHT_RU_996_484_242;

	default:

		return ATH12K_EHT_RU_INVALID;

	}

}



static inline u32

hal_rx_ul_ofdma_ru_size_to_width(enum ath12k_eht_ru_size ru_size)

{

	switch (ru_size) {

	case ATH12K_EHT_RU_26:

		return RU_26;

	case ATH12K_EHT_RU_52:

		return RU_52;

	case ATH12K_EHT_RU_52_26:

		return RU_52_26;

	case ATH12K_EHT_RU_106:

		return RU_106;

	case ATH12K_EHT_RU_106_26:

		return RU_106_26;

	case ATH12K_EHT_RU_242:

		return RU_242;

	case ATH12K_EHT_RU_484:

		return RU_484;

	case ATH12K_EHT_RU_484_242:

		return RU_484_242;

	case ATH12K_EHT_RU_996:

		return RU_996;

	case ATH12K_EHT_RU_996_484:

		return RU_996_484;

	case ATH12K_EHT_RU_996_484_242:

		return RU_996_484_242;

	case ATH12K_EHT_RU_996x2:

		return RU_2X996;

	case ATH12K_EHT_RU_996x2_484:

		return RU_2X996_484;

	case ATH12K_EHT_RU_996x3:

		return RU_3X996;

	case ATH12K_EHT_RU_996x3_484:

		return RU_3X996_484;

	case ATH12K_EHT_RU_996x4:

		return RU_4X996;

	default:

		return RU_INVALID;

	}

}



static void

ath12k_wifi7_dp_mon_hal_rx_parse_user_info(const struct hal_receive_user_info *rx_usr_info,

					   u16 user_id,

					   struct hal_rx_mon_ppdu_info *ppdu_info)

{

	struct hal_rx_user_status *mon_rx_user_status = NULL;

	struct hal_rx_radiotap_eht *eht = &ppdu_info->eht_info.eht;

	enum ath12k_eht_ru_size rtap_ru_size = ATH12K_EHT_RU_INVALID;

	u32 ru_width, reception_type, ru_index = HAL_EHT_RU_INVALID;

	u32 ru_type_80_0, ru_start_index_80_0;

	u32 ru_type_80_1, ru_start_index_80_1;

	u32 ru_type_80_2, ru_start_index_80_2;

	u32 ru_type_80_3, ru_start_index_80_3;

	u32 ru_size = 0, num_80mhz_with_ru = 0;

	u64 ru_index_320mhz = 0;

	u32 ru_index_per80mhz;



	reception_type = le32_get_bits(rx_usr_info->info0,

				       HAL_RX_USR_INFO0_RECEPTION_TYPE);



	switch (reception_type) {

	case HAL_RECEPTION_TYPE_SU:

		ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;

		break;

	case HAL_RECEPTION_TYPE_DL_MU_MIMO:

	case HAL_RECEPTION_TYPE_UL_MU_MIMO:

		ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO;

		break;

	case HAL_RECEPTION_TYPE_DL_MU_OFMA:

	case HAL_RECEPTION_TYPE_UL_MU_OFDMA:

		ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_OFDMA;

		break;

	case HAL_RECEPTION_TYPE_DL_MU_OFDMA_MIMO:

	case HAL_RECEPTION_TYPE_UL_MU_OFDMA_MIMO:

		ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO;

	}



	ppdu_info->is_stbc = le32_get_bits(rx_usr_info->info0, HAL_RX_USR_INFO0_STBC);

	ppdu_info->ldpc = le32_get_bits(rx_usr_info->info2, HAL_RX_USR_INFO2_LDPC);

	ppdu_info->dcm = le32_get_bits(rx_usr_info->info2, HAL_RX_USR_INFO2_STA_DCM);

	ppdu_info->bw = le32_get_bits(rx_usr_info->info1, HAL_RX_USR_INFO1_RX_BW);

	ppdu_info->mcs = le32_get_bits(rx_usr_info->info1, HAL_RX_USR_INFO1_MCS);

	ppdu_info->nss = le32_get_bits(rx_usr_info->info2, HAL_RX_USR_INFO2_NSS) + 1;



	if (user_id < HAL_MAX_UL_MU_USERS) {

		mon_rx_user_status = &ppdu_info->userstats[user_id];

		mon_rx_user_status->mcs = ppdu_info->mcs;

		mon_rx_user_status->nss = ppdu_info->nss;

	}



	if (!(ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_MIMO ||

	      ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_OFDMA ||

	      ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO))

		return;



	/* RU allocation present only for OFDMA reception */

	ru_type_80_0 = le32_get_bits(rx_usr_info->info2, HAL_RX_USR_INFO2_RU_TYPE_80_0);

	ru_start_index_80_0 = le32_get_bits(rx_usr_info->info3,

					    HAL_RX_USR_INFO3_RU_START_IDX_80_0);

	if (ru_type_80_0 != HAL_EHT_RU_NONE) {

		ru_size += ru_type_80_0;

		ru_index_per80mhz = ru_start_index_80_0;

		ru_index = ru_index_per80mhz;

		ru_index_320mhz |= HAL_RU_PER80(ru_type_80_0, 0, ru_index_per80mhz);

		num_80mhz_with_ru++;

	}



	ru_type_80_1 = le32_get_bits(rx_usr_info->info2, HAL_RX_USR_INFO2_RU_TYPE_80_1);

	ru_start_index_80_1 = le32_get_bits(rx_usr_info->info3,

					    HAL_RX_USR_INFO3_RU_START_IDX_80_1);

	if (ru_type_80_1 != HAL_EHT_RU_NONE) {

		ru_size += ru_type_80_1;

		ru_index_per80mhz = ru_start_index_80_1;

		ru_index = ru_index_per80mhz;

		ru_index_320mhz |= HAL_RU_PER80(ru_type_80_1, 1, ru_index_per80mhz);

		num_80mhz_with_ru++;

	}



	ru_type_80_2 = le32_get_bits(rx_usr_info->info2, HAL_RX_USR_INFO2_RU_TYPE_80_2);

	ru_start_index_80_2 = le32_get_bits(rx_usr_info->info3,

					    HAL_RX_USR_INFO3_RU_START_IDX_80_2);

	if (ru_type_80_2 != HAL_EHT_RU_NONE) {

		ru_size += ru_type_80_2;

		ru_index_per80mhz = ru_start_index_80_2;

		ru_index = ru_index_per80mhz;

		ru_index_320mhz |= HAL_RU_PER80(ru_type_80_2, 2, ru_index_per80mhz);

		num_80mhz_with_ru++;

	}



	ru_type_80_3 = le32_get_bits(rx_usr_info->info2, HAL_RX_USR_INFO2_RU_TYPE_80_3);

	ru_start_index_80_3 = le32_get_bits(rx_usr_info->info2,

					    HAL_RX_USR_INFO3_RU_START_IDX_80_3);

	if (ru_type_80_3 != HAL_EHT_RU_NONE) {

		ru_size += ru_type_80_3;

		ru_index_per80mhz = ru_start_index_80_3;

		ru_index = ru_index_per80mhz;

		ru_index_320mhz |= HAL_RU_PER80(ru_type_80_3, 3, ru_index_per80mhz);

		num_80mhz_with_ru++;

	}



	if (num_80mhz_with_ru > 1) {

		/* Calculate the MRU index */

		switch (ru_index_320mhz) {

		case HAL_EHT_RU_996_484_0:

		case HAL_EHT_RU_996x2_484_0:

		case HAL_EHT_RU_996x3_484_0:

			ru_index = 0;

			break;

		case HAL_EHT_RU_996_484_1:

		case HAL_EHT_RU_996x2_484_1:

		case HAL_EHT_RU_996x3_484_1:

			ru_index = 1;

			break;

		case HAL_EHT_RU_996_484_2:

		case HAL_EHT_RU_996x2_484_2:

		case HAL_EHT_RU_996x3_484_2:

			ru_index = 2;

			break;

		case HAL_EHT_RU_996_484_3:

		case HAL_EHT_RU_996x2_484_3:

		case HAL_EHT_RU_996x3_484_3:

			ru_index = 3;

			break;

		case HAL_EHT_RU_996_484_4:

		case HAL_EHT_RU_996x2_484_4:

		case HAL_EHT_RU_996x3_484_4:

			ru_index = 4;

			break;

		case HAL_EHT_RU_996_484_5:

		case HAL_EHT_RU_996x2_484_5:

		case HAL_EHT_RU_996x3_484_5:

			ru_index = 5;

			break;

		case HAL_EHT_RU_996_484_6:

		case HAL_EHT_RU_996x2_484_6:

		case HAL_EHT_RU_996x3_484_6:

			ru_index = 6;

			break;

		case HAL_EHT_RU_996_484_7:

		case HAL_EHT_RU_996x2_484_7:

		case HAL_EHT_RU_996x3_484_7:

			ru_index = 7;

			break;

		case HAL_EHT_RU_996x2_484_8:

			ru_index = 8;

			break;

		case HAL_EHT_RU_996x2_484_9:

			ru_index = 9;

			break;

		case HAL_EHT_RU_996x2_484_10:

			ru_index = 10;

			break;

		case HAL_EHT_RU_996x2_484_11:

			ru_index = 11;

			break;

		default:

			ru_index = HAL_EHT_RU_INVALID;

			break;

		}



		ru_size += 4;

	}



	rtap_ru_size = hal_rx_mon_hal_ru_size_to_ath12k_ru_size(ru_size);

	if (rtap_ru_size != ATH12K_EHT_RU_INVALID) {

		u32 known, data;



		known = __le32_to_cpu(eht->known);

		known |= IEEE80211_RADIOTAP_EHT_KNOWN_RU_MRU_SIZE_OM;

		eht->known = cpu_to_le32(known);



		data = __le32_to_cpu(eht->data[1]);

		data |=	u32_encode_bits(rtap_ru_size,

					IEEE80211_RADIOTAP_EHT_DATA1_RU_SIZE);

		eht->data[1] = cpu_to_le32(data);

	}



	if (ru_index != HAL_EHT_RU_INVALID) {

		u32 known, data;



		known = __le32_to_cpu(eht->known);

		known |= IEEE80211_RADIOTAP_EHT_KNOWN_RU_MRU_INDEX_OM;

		eht->known = cpu_to_le32(known);



		data = __le32_to_cpu(eht->data[1]);

		data |=	u32_encode_bits(rtap_ru_size,

					IEEE80211_RADIOTAP_EHT_DATA1_RU_INDEX);

		eht->data[1] = cpu_to_le32(data);

	}



	if (mon_rx_user_status && ru_index != HAL_EHT_RU_INVALID &&

	    rtap_ru_size != ATH12K_EHT_RU_INVALID) {

		mon_rx_user_status->ul_ofdma_ru_start_index = ru_index;

		mon_rx_user_status->ul_ofdma_ru_size = rtap_ru_size;



		ru_width = hal_rx_ul_ofdma_ru_size_to_width(rtap_ru_size);



		mon_rx_user_status->ul_ofdma_ru_width = ru_width;

		mon_rx_user_status->ofdma_info_valid = 1;

	}

}



static void

ath12k_wifi7_dp_mon_parse_l_sig_b(const struct hal_rx_lsig_b_info *lsigb,

				  struct hal_rx_mon_ppdu_info *ppdu_info)
@@ -1196,8 +1544,8 @@ ath12k_wifi7_dp_mon_rx_parse_status_tlv(struct ath12k_pdev_dp *dp_pdev, 


			ppdu_info->num_users += 1;



			ath12k_dp_mon_rx_handle_ofdma_info(eu_stats, rxuser_stats);

			ath12k_dp_mon_rx_populate_mu_user_info(eu_stats, ppdu_info,

			ath12k_wifi7_dp_mon_rx_handle_ofdma_info(eu_stats, rxuser_stats);

			ath12k_wifi7_dp_mon_rx_populate_mu_user_info(eu_stats, ppdu_info,

								     rxuser_stats);

		}

		ppdu_info->mpdu_fcs_ok_bitmap[0] = __le32_to_cpu(eu_stats->rsvd1[0]);
@@ -1277,7 +1625,7 @@ ath12k_wifi7_dp_mon_rx_parse_status_tlv(struct ath12k_pdev_dp *dp_pdev, 
		break;

	}

	case HAL_RX_PPDU_START_USER_INFO:

		ath12k_dp_mon_hal_rx_parse_user_info(tlv_data, userid, ppdu_info);

		ath12k_wifi7_dp_mon_hal_rx_parse_user_info(tlv_data, userid, ppdu_info);

		break;



	case HAL_RXPCU_PPDU_END_INFO: {