Commit 5e74df2f authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'x86-urgent-2024-03-24' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 fixes from Thomas Gleixner:

 - Ensure that the encryption mask at boot is properly propagated on
   5-level page tables, otherwise the PGD entry is incorrectly set to
   non-encrypted, which causes system crashes during boot.

 - Undo the deferred 5-level page table setup as it cannot work with
   memory encryption enabled.

 - Prevent inconsistent XFD state on CPU hotplug, where the MSR is reset
   to the default value but the cached variable is not, so subsequent
   comparisons might yield the wrong result and as a consequence the
   result prevents updating the MSR.

 - Register the local APIC address only once in the MPPARSE enumeration
   to prevent triggering the related WARN_ONs() in the APIC and topology
   code.

 - Handle the case where no APIC is found gracefully by registering a
   fake APIC in the topology code. That makes all related topology
   functions work correctly and does not affect the actual APIC driver
   code at all.

 - Don't evaluate logical IDs during early boot as the local APIC IDs
   are not yet enumerated and the invoked function returns an error
   code. Nothing requires the logical IDs before the final CPUID
   enumeration takes place, which happens after the enumeration.

 - Cure the fallout of the per CPU rework on UP which misplaced the
   copying of boot_cpu_data to per CPU data so that the final update to
   boot_cpu_data got lost which caused inconsistent state and boot
   crashes.

 - Use copy_from_kernel_nofault() in the kprobes setup as there is no
   guarantee that the address can be safely accessed.

 - Reorder struct members in struct saved_context to work around another
   kmemleak false positive

 - Remove the buggy code which tries to update the E820 kexec table for
   setup_data as that is never passed to the kexec kernel.

 - Update the resource control documentation to use the proper units.

 - Fix a Kconfig warning observed with tinyconfig

* tag 'x86-urgent-2024-03-24' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/boot/64: Move 5-level paging global variable assignments back
  x86/boot/64: Apply encryption mask to 5-level pagetable update
  x86/cpu: Add model number for another Intel Arrow Lake mobile processor
  x86/fpu: Keep xfd_state in sync with MSR_IA32_XFD
  Documentation/x86: Document that resctrl bandwidth control units are MiB
  x86/mpparse: Register APIC address only once
  x86/topology: Handle the !APIC case gracefully
  x86/topology: Don't evaluate logical IDs during early boot
  x86/cpu: Ensure that CPU info updates are propagated on UP
  kprobes/x86: Use copy_from_kernel_nofault() to read from unsafe address
  x86/pm: Work around false positive kmemleak report in msr_build_context()
  x86/kexec: Do not update E820 kexec table for setup_data
  x86/config: Fix warning for 'make ARCH=x86_64 tinyconfig'
parents b136f68e 9843231c

Documentation/arch/x86/resctrl.rst

+4 −4
Original line number Diff line number Diff line
@@ -45,7 +45,7 @@ mount options are: 
	Enable code/data prioritization in L2 cache allocations.

"mba_MBps":

	Enable the MBA Software Controller(mba_sc) to specify MBA

	bandwidth in MBps

	bandwidth in MiBps

"debug":

	Make debug files accessible. Available debug files are annotated with

	"Available only with debug option".
@@ -526,7 +526,7 @@ threads start using more cores in an rdtgroup, the actual bandwidth may 
increase or vary although user specified bandwidth percentage is same.



In order to mitigate this and make the interface more user friendly,

resctrl added support for specifying the bandwidth in MBps as well.  The

resctrl added support for specifying the bandwidth in MiBps as well.  The

kernel underneath would use a software feedback mechanism or a "Software

Controller(mba_sc)" which reads the actual bandwidth using MBM counters

and adjust the memory bandwidth percentages to ensure::
@@ -573,13 +573,13 @@ Memory b/w domain is L3 cache. 


	MB:<cache_id0>=bandwidth0;<cache_id1>=bandwidth1;...



Memory bandwidth Allocation specified in MBps

Memory bandwidth Allocation specified in MiBps

---------------------------------------------



Memory bandwidth domain is L3 cache.

::



	MB:<cache_id0>=bw_MBps0;<cache_id1>=bw_MBps1;...

	MB:<cache_id0>=bw_MiBps0;<cache_id1>=bw_MiBps1;...



Slow Memory Bandwidth Allocation (SMBA)

---------------------------------------

arch/x86/configs/tiny.config

+1 −0
Original line number Diff line number Diff line 
CONFIG_NOHIGHMEM=y

# CONFIG_HIGHMEM4G is not set

# CONFIG_HIGHMEM64G is not set

# CONFIG_UNWINDER_ORC is not set

CONFIG_UNWINDER_GUESS=y

# CONFIG_UNWINDER_FRAME_POINTER is not set

arch/x86/include/asm/intel-family.h

+1 −0
Original line number Diff line number Diff line
@@ -127,6 +127,7 @@ 


#define INTEL_FAM6_ARROWLAKE_H		0xC5

#define INTEL_FAM6_ARROWLAKE		0xC6

#define INTEL_FAM6_ARROWLAKE_U		0xB5



#define INTEL_FAM6_LUNARLAKE_M		0xBD

arch/x86/include/asm/suspend_32.h

+5 −5
Original line number Diff line number Diff line
@@ -12,11 +12,6 @@ 


/* image of the saved processor state */

struct saved_context {

	/*

	 * On x86_32, all segment registers except gs are saved at kernel

	 * entry in pt_regs.

	 */

	u16 gs;

	unsigned long cr0, cr2, cr3, cr4;

	u64 misc_enable;

	struct saved_msrs saved_msrs;
@@ -27,6 +22,11 @@ struct saved_context { 
	unsigned long tr;

	unsigned long safety;

	unsigned long return_address;

	/*

	 * On x86_32, all segment registers except gs are saved at kernel

	 * entry in pt_regs.

	 */

	u16 gs;

	bool misc_enable_saved;

} __attribute__((packed));

arch/x86/kernel/cpu/common.c

+9 −0
Original line number Diff line number Diff line
@@ -2307,6 +2307,8 @@ void arch_smt_update(void) 


void __init arch_cpu_finalize_init(void)

{

	struct cpuinfo_x86 *c = this_cpu_ptr(&cpu_info);



	identify_boot_cpu();



	select_idle_routine();
@@ -2345,6 +2347,13 @@ void __init arch_cpu_finalize_init(void) 
	fpu__init_system();

	fpu__init_cpu();



	/*

	 * Ensure that access to the per CPU representation has the initial

	 * boot CPU configuration.

	 */

	*c = boot_cpu_data;

	c->initialized = true;



	alternative_instructions();



	if (IS_ENABLED(CONFIG_X86_64)) {