Commit 5e830d3c authored by Sunyeal Hong's avatar Sunyeal Hong Committed by Krzysztof Kozlowski
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clk: samsung: exynosautov920: add peric1, misc and hsi0/1 clock support 



Register compatible and cmu_info data to support clocks.
CMU_PERIC1, this provides clocks for USI09 ~ USI17, USI_I2C and USI_I3C.
CMU_MISC, this provides clocks for MISC, GIC and OTP.
CMU_HSI0, this provides clocks for PCIE.
CMU_HSI1, this provides clocks for USB and MMC.

Signed-off-by: default avatarSunyeal Hong <sunyeal.hong@samsung.com>
Link: https://lore.kernel.org/r/20241009042110.2379903-3-sunyeal.hong@samsung.com


Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
parent ac08b52a

drivers/clk/samsung/clk-exynosautov920.c

+289 −0
Original line number Diff line number Diff line
@@ -19,6 +19,10 @@ 
/* NOTE: Must be equal to the last clock ID increased by one */

#define CLKS_NR_TOP			(DOUT_CLKCMU_TAA_NOC + 1)

#define CLKS_NR_PERIC0			(CLK_DOUT_PERIC0_I3C + 1)

#define CLKS_NR_PERIC1			(CLK_DOUT_PERIC1_I3C + 1)

#define CLKS_NR_MISC			(CLK_DOUT_MISC_OSC_DIV2 + 1)

#define CLKS_NR_HSI0			(CLK_DOUT_HSI0_PCIE_APB + 1)

#define CLKS_NR_HSI1			(CLK_MOUT_HSI1_USBDRD + 1)



/* ---- CMU_TOP ------------------------------------------------------------ */
@@ -974,6 +978,8 @@ static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initcon 
		"mout_shared5_pll", 1, 3, 0),

	FFACTOR(DOUT_SHARED5_DIV4, "dout_shared5_div4",

		"mout_shared5_pll", 1, 4, 0),

	FFACTOR(DOUT_TCXO_DIV2, "dout_tcxo_div2",

		"oscclk", 1, 2, 0),

};



static const struct samsung_cmu_info top_cmu_info __initconst = {
@@ -1139,6 +1145,277 @@ static const struct samsung_cmu_info peric0_cmu_info __initconst = { 
	.clk_name		= "noc",

};



/* ---- CMU_PERIC1 --------------------------------------------------------- */



/* Register Offset definitions for CMU_PERIC1 (0x10C00000) */

#define PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER	0x600

#define PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER	0x610

#define CLK_CON_MUX_MUX_CLK_PERIC1_I3C		0x1000

#define CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI	0x1004

#define CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI	0x1008

#define CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI	0x100c

#define CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI	0x1010

#define CLK_CON_MUX_MUX_CLK_PERIC1_USI13_USI	0x1014

#define CLK_CON_MUX_MUX_CLK_PERIC1_USI14_USI	0x1018

#define CLK_CON_MUX_MUX_CLK_PERIC1_USI15_USI	0x101c

#define CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI	0x1020

#define CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI	0x1024

#define CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C	0x1028

#define CLK_CON_DIV_DIV_CLK_PERIC1_I3C		0x1800

#define CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI	0x1804

#define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI	0x1808

#define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI	0x180c

#define CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI	0x1810

#define CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI	0x1814

#define CLK_CON_DIV_DIV_CLK_PERIC1_USI14_USI	0x1818

#define CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI	0x181c

#define CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI	0x1820

#define CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI	0x1824

#define CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C	0x1828



static const unsigned long peric1_clk_regs[] __initconst = {

	PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER,

	PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER,

	CLK_CON_MUX_MUX_CLK_PERIC1_I3C,

	CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI,

	CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI,

	CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI,

	CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI,

	CLK_CON_MUX_MUX_CLK_PERIC1_USI13_USI,

	CLK_CON_MUX_MUX_CLK_PERIC1_USI14_USI,

	CLK_CON_MUX_MUX_CLK_PERIC1_USI15_USI,

	CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI,

	CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI,

	CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C,

	CLK_CON_DIV_DIV_CLK_PERIC1_I3C,

	CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI,

	CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,

	CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,

	CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI,

	CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI,

	CLK_CON_DIV_DIV_CLK_PERIC1_USI14_USI,

	CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI,

	CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI,

	CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI,

	CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C,

};



/* List of parent clocks for Muxes in CMU_PERIC1 */

PNAME(mout_peric1_ip_user_p) = { "oscclk", "dout_clkcmu_peric1_ip" };

PNAME(mout_peric1_noc_user_p) = { "oscclk", "dout_clkcmu_peric1_noc" };

PNAME(mout_peric1_usi_p) = { "oscclk", "mout_peric1_ip_user" };



static const struct samsung_mux_clock peric1_mux_clks[] __initconst = {

	MUX(CLK_MOUT_PERIC1_IP_USER, "mout_peric1_ip_user",

	    mout_peric1_ip_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER, 4, 1),

	MUX(CLK_MOUT_PERIC1_NOC_USER, "mout_peric1_noc_user",

	    mout_peric1_noc_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER, 4, 1),

	/* USI09 ~ USI17 */

	MUX(CLK_MOUT_PERIC1_USI09_USI, "mout_peric1_usi09_usi",

	    mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI, 0, 1),

	MUX(CLK_MOUT_PERIC1_USI10_USI, "mout_peric1_usi10_usi",

	    mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI, 0, 1),

	MUX(CLK_MOUT_PERIC1_USI11_USI, "mout_peric1_usi11_usi",

	    mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI, 0, 1),

	MUX(CLK_MOUT_PERIC1_USI12_USI, "mout_peric1_usi12_usi",

	    mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI, 0, 1),

	MUX(CLK_MOUT_PERIC1_USI13_USI, "mout_peric1_usi13_usi",

	    mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI13_USI, 0, 1),

	MUX(CLK_MOUT_PERIC1_USI14_USI, "mout_peric1_usi14_usi",

	    mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI14_USI, 0, 1),

	MUX(CLK_MOUT_PERIC1_USI15_USI, "mout_peric1_usi15_usi",

	    mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI15_USI, 0, 1),

	MUX(CLK_MOUT_PERIC1_USI16_USI, "mout_peric1_usi16_usi",

	    mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI, 0, 1),

	MUX(CLK_MOUT_PERIC1_USI17_USI, "mout_peric1_usi17_usi",

	    mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI, 0, 1),

	/* USI_I2C */

	MUX(CLK_MOUT_PERIC1_USI_I2C, "mout_peric1_usi_i2c",

	    mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C, 0, 1),

	/* USI_I3C */

	MUX(CLK_MOUT_PERIC1_I3C, "mout_peric1_i3c",

	    mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_I3C, 0, 1),

};



static const struct samsung_div_clock peric1_div_clks[] __initconst = {

	/* USI09 ~ USI17 */

	DIV(CLK_DOUT_PERIC1_USI09_USI, "dout_peric1_usi09_usi",

	    "mout_peric1_usi09_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI,

	    0, 4),

	DIV(CLK_DOUT_PERIC1_USI10_USI, "dout_peric1_usi10_usi",

	    "mout_peric1_usi10_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,

	    0, 4),

	DIV(CLK_DOUT_PERIC1_USI11_USI, "dout_peric1_usi11_usi",

	    "mout_peric1_usi11_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,

	    0, 4),

	DIV(CLK_DOUT_PERIC1_USI12_USI, "dout_peric1_usi12_usi",

	    "mout_peric1_usi12_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI,

	    0, 4),

	DIV(CLK_DOUT_PERIC1_USI13_USI, "dout_peric1_usi13_usi",

	    "mout_peric1_usi13_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI,

	    0, 4),

	DIV(CLK_DOUT_PERIC1_USI14_USI, "dout_peric1_usi14_usi",

	    "mout_peric1_usi14_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI14_USI,

	    0, 4),

	DIV(CLK_DOUT_PERIC1_USI15_USI, "dout_peric1_usi15_usi",

	    "mout_peric1_usi15_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI,

	    0, 4),

	DIV(CLK_DOUT_PERIC1_USI16_USI, "dout_peric1_usi16_usi",

	    "mout_peric1_usi16_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI,

	    0, 4),

	DIV(CLK_DOUT_PERIC1_USI17_USI, "dout_peric1_usi17_usi",

	    "mout_peric1_usi17_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI,

	    0, 4),

	/* USI_I2C */

	DIV(CLK_DOUT_PERIC1_USI_I2C, "dout_peric1_usi_i2c",

	    "mout_peric1_usi_i2c", CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C, 0, 4),

	/* USI_I3C */

	DIV(CLK_DOUT_PERIC1_I3C, "dout_peric1_i3c",

	    "mout_peric1_i3c", CLK_CON_DIV_DIV_CLK_PERIC1_I3C, 0, 4),

};



static const struct samsung_cmu_info peric1_cmu_info __initconst = {

	.mux_clks		= peric1_mux_clks,

	.nr_mux_clks		= ARRAY_SIZE(peric1_mux_clks),

	.div_clks		= peric1_div_clks,

	.nr_div_clks		= ARRAY_SIZE(peric1_div_clks),

	.nr_clk_ids		= CLKS_NR_PERIC1,

	.clk_regs		= peric1_clk_regs,

	.nr_clk_regs		= ARRAY_SIZE(peric1_clk_regs),

	.clk_name		= "noc",

};



/* ---- CMU_MISC --------------------------------------------------------- */



/* Register Offset definitions for CMU_MISC (0x10020000) */

#define PLL_CON0_MUX_CLKCMU_MISC_NOC_USER	0x600

#define CLK_CON_MUX_MUX_CLK_MISC_GIC		0x1000

#define CLK_CON_DIV_CLKCMU_OTP			0x1800

#define CLK_CON_DIV_DIV_CLK_MISC_NOCP		0x1804

#define CLK_CON_DIV_DIV_CLK_MISC_OSC_DIV2	0x1808



static const unsigned long misc_clk_regs[] __initconst = {

	PLL_CON0_MUX_CLKCMU_MISC_NOC_USER,

	CLK_CON_MUX_MUX_CLK_MISC_GIC,

	CLK_CON_DIV_CLKCMU_OTP,

	CLK_CON_DIV_DIV_CLK_MISC_NOCP,

	CLK_CON_DIV_DIV_CLK_MISC_OSC_DIV2,

};



/* List of parent clocks for Muxes in CMU_MISC */

PNAME(mout_misc_noc_user_p) = { "oscclk", "dout_clkcmu_misc_noc" };

PNAME(mout_misc_gic_p) = { "dout_misc_nocp", "oscclk" };



static const struct samsung_mux_clock misc_mux_clks[] __initconst = {

	MUX(CLK_MOUT_MISC_NOC_USER, "mout_misc_noc_user",

	    mout_misc_noc_user_p, PLL_CON0_MUX_CLKCMU_MISC_NOC_USER, 4, 1),

	MUX(CLK_MOUT_MISC_GIC, "mout_misc_gic",

	    mout_misc_gic_p, CLK_CON_MUX_MUX_CLK_MISC_GIC, 0, 1),

};



static const struct samsung_div_clock misc_div_clks[] __initconst = {

	DIV(CLK_DOUT_MISC_NOCP, "dout_misc_nocp",

	    "mout_misc_noc_user", CLK_CON_DIV_DIV_CLK_MISC_NOCP,

	    0, 3),

};



static const struct samsung_fixed_factor_clock misc_fixed_factor_clks[] __initconst = {

	FFACTOR(CLK_DOUT_MISC_OTP, "dout_misc_otp",

		"oscclk", 1, 10, 0),

	FFACTOR(CLK_DOUT_MISC_OSC_DIV2, "dout_misc_osc_div2",

		"oscclk", 1, 2, 0),

};



static const struct samsung_cmu_info misc_cmu_info __initconst = {

	.mux_clks		= misc_mux_clks,

	.nr_mux_clks		= ARRAY_SIZE(misc_mux_clks),

	.div_clks		= misc_div_clks,

	.nr_div_clks		= ARRAY_SIZE(misc_div_clks),

	.fixed_factor_clks	= misc_fixed_factor_clks,

	.nr_fixed_factor_clks	= ARRAY_SIZE(misc_fixed_factor_clks),

	.nr_clk_ids		= CLKS_NR_MISC,

	.clk_regs		= misc_clk_regs,

	.nr_clk_regs		= ARRAY_SIZE(misc_clk_regs),

	.clk_name		= "noc",

};



/* ---- CMU_HSI0 --------------------------------------------------------- */



/* Register Offset definitions for CMU_HSI0 (0x16000000) */

#define PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER	0x600

#define CLK_CON_DIV_DIV_CLK_HSI0_PCIE_APB	0x1800



static const unsigned long hsi0_clk_regs[] __initconst = {

	PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER,

	CLK_CON_DIV_DIV_CLK_HSI0_PCIE_APB,

};



/* List of parent clocks for Muxes in CMU_HSI0 */

PNAME(mout_hsi0_noc_user_p) = { "oscclk", "dout_clkcmu_hsi0_noc" };



static const struct samsung_mux_clock hsi0_mux_clks[] __initconst = {

	MUX(CLK_MOUT_HSI0_NOC_USER, "mout_hsi0_noc_user",

	    mout_hsi0_noc_user_p, PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER, 4, 1),

};



static const struct samsung_div_clock hsi0_div_clks[] __initconst = {

	DIV(CLK_DOUT_HSI0_PCIE_APB, "dout_hsi0_pcie_apb",

	    "mout_hsi0_noc_user", CLK_CON_DIV_DIV_CLK_HSI0_PCIE_APB,

	    0, 4),

};



static const struct samsung_cmu_info hsi0_cmu_info __initconst = {

	.mux_clks		= hsi0_mux_clks,

	.nr_mux_clks		= ARRAY_SIZE(hsi0_mux_clks),

	.div_clks		= hsi0_div_clks,

	.nr_div_clks		= ARRAY_SIZE(hsi0_div_clks),

	.nr_clk_ids		= CLKS_NR_HSI0,

	.clk_regs		= hsi0_clk_regs,

	.nr_clk_regs		= ARRAY_SIZE(hsi0_clk_regs),

	.clk_name		= "noc",

};



/* ---- CMU_HSI1 --------------------------------------------------------- */



/* Register Offset definitions for CMU_HSI1 (0x16400000) */

#define PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER	0x600

#define PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER	0x610

#define PLL_CON0_MUX_CLKCMU_HSI1_USBDRD_USER	0x620

#define CLK_CON_MUX_MUX_CLK_HSI1_USBDRD		0x1000



static const unsigned long hsi1_clk_regs[] __initconst = {

	PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER,

	PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER,

	PLL_CON0_MUX_CLKCMU_HSI1_USBDRD_USER,

	CLK_CON_MUX_MUX_CLK_HSI1_USBDRD,

};



/* List of parent clocks for Muxes in CMU_HSI1 */

PNAME(mout_hsi1_mmc_card_user_p) = {"oscclk", "dout_clkcmu_hsi1_mmc_card"};

PNAME(mout_hsi1_noc_user_p) = { "oscclk", "dout_clkcmu_hsi1_noc" };

PNAME(mout_hsi1_usbdrd_user_p) = { "oscclk", "mout_clkcmu_hsi1_usbdrd" };

PNAME(mout_hsi1_usbdrd_p) = { "dout_tcxo_div2", "mout_hsi1_usbdrd_user" };



static const struct samsung_mux_clock hsi1_mux_clks[] __initconst = {

	MUX(CLK_MOUT_HSI1_MMC_CARD_USER, "mout_hsi1_mmc_card_user",

	    mout_hsi1_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER, 4, 1),

	MUX(CLK_MOUT_HSI1_NOC_USER, "mout_hsi1_noc_user",

	    mout_hsi1_noc_user_p, PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER, 4, 1),

	MUX(CLK_MOUT_HSI1_USBDRD_USER, "mout_hsi1_usbdrd_user",

	    mout_hsi1_usbdrd_user_p, PLL_CON0_MUX_CLKCMU_HSI1_USBDRD_USER, 4, 1),

	MUX(CLK_MOUT_HSI1_USBDRD, "mout_hsi1_usbdrd",

	    mout_hsi1_usbdrd_p, CLK_CON_MUX_MUX_CLK_HSI1_USBDRD, 4, 1),

};



static const struct samsung_cmu_info hsi1_cmu_info __initconst = {

	.mux_clks		= hsi1_mux_clks,

	.nr_mux_clks		= ARRAY_SIZE(hsi1_mux_clks),

	.nr_clk_ids		= CLKS_NR_HSI1,

	.clk_regs		= hsi1_clk_regs,

	.nr_clk_regs		= ARRAY_SIZE(hsi1_clk_regs),

	.clk_name		= "noc",

};



static int __init exynosautov920_cmu_probe(struct platform_device *pdev)

{

	const struct samsung_cmu_info *info;
@@ -1154,6 +1431,18 @@ static const struct of_device_id exynosautov920_cmu_of_match[] = { 
	{

		.compatible = "samsung,exynosautov920-cmu-peric0",

		.data = &peric0_cmu_info,

	}, {

		 .compatible = "samsung,exynosautov920-cmu-peric1",

		 .data = &peric1_cmu_info,

	}, {

		 .compatible = "samsung,exynosautov920-cmu-misc",

		 .data = &misc_cmu_info,

	}, {

		.compatible = "samsung,exynosautov920-cmu-hsi0",

		.data = &hsi0_cmu_info,

	}, {

		.compatible = "samsung,exynosautov920-cmu-hsi1",

		.data = &hsi1_cmu_info,

	},

	{ }

};