Commit 5eb83fc1 authored by Abel Vesa's avatar Abel Vesa Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: x1e80100: Add PCIe nodes 



Add nodes for PCIe 4 and 6 controllers and their PHYs for X1E80100 platform.

Co-developed-by: default avatarSibi Sankar <quic_sibis@quicinc.com>
Signed-off-by: default avatarSibi Sankar <quic_sibis@quicinc.com>
Co-developed-by: default avatarRajendra Nayak <quic_rjendra@quicinc.com>
Signed-off-by: default avatarRajendra Nayak <quic_rjendra@quicinc.com>
Signed-off-by: default avatarAbel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20240129-x1e80100-dts-missing-nodes-v6-7-2c0e691cfa3b@linaro.org


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 4af46b7b

arch/arm64/boot/dts/qcom/x1e80100.dtsi

+240 −2
Original line number Diff line number Diff line
@@ -740,9 +740,9 @@ gcc: clock-controller@100000 { 
			clocks = <&bi_tcxo_div2>,

				 <&sleep_clk>,

				 <0>,

				 <&pcie4_phy>,

				 <0>,

				 <0>,

				 <0>,

				 <&pcie6a_phy>,

				 <0>,

				 <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,

				 <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
@@ -2730,6 +2730,244 @@ mmss_noc: interconnect@1780000 { 
			#interconnect-cells = <2>;

		};



		pcie6a: pci@1bf8000 {

			device_type = "pci";

			compatible = "qcom,pcie-x1e80100";

			reg = <0 0x01bf8000 0 0x3000>,

			      <0 0x70000000 0 0xf1d>,

			      <0 0x70000f20 0 0xa8>,

			      <0 0x70001000 0 0x1000>,

			      <0 0x70100000 0 0x100000>;

			reg-names = "parf",

				    "dbi",

				    "elbi",

				    "atu",

				    "config";

			#address-cells = <3>;

			#size-cells = <2>;

			ranges = <0x01000000 0 0x00000000 0 0x70200000 0 0x100000>,

				 <0x02000000 0 0x70300000 0 0x70300000 0 0x3d00000>;

			bus-range = <0 0xff>;



			dma-coherent;



			linux,pci-domain = <7>;

			num-lanes = <2>;



			interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "msi0",

					  "msi1",

					  "msi2",

					  "msi3",

					  "msi4",

					  "msi5",

					  "msi6",

					  "msi7";



			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 0x7>;

			interrupt-map = <0 0 0 1 &intc 0 0 0 843 IRQ_TYPE_LEVEL_HIGH>,

					<0 0 0 2 &intc 0 0 0 844 IRQ_TYPE_LEVEL_HIGH>,

					<0 0 0 3 &intc 0 0 0 845 IRQ_TYPE_LEVEL_HIGH>,

					<0 0 0 4 &intc 0 0 0 772 IRQ_TYPE_LEVEL_HIGH>;



			clocks = <&gcc GCC_PCIE_6A_AUX_CLK>,

				 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>,

				 <&gcc GCC_PCIE_6A_MSTR_AXI_CLK>,

				 <&gcc GCC_PCIE_6A_SLV_AXI_CLK>,

				 <&gcc GCC_PCIE_6A_SLV_Q2A_AXI_CLK>,

				 <&gcc GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK>,

				 <&gcc GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK>;

			clock-names = "aux",

				      "cfg",

				      "bus_master",

				      "bus_slave",

				      "slave_q2a",

				      "noc_aggr",

				      "cnoc_sf_axi";



			assigned-clocks = <&gcc GCC_PCIE_6A_AUX_CLK>;

			assigned-clock-rates = <19200000>;



			interconnects = <&pcie_south_anoc MASTER_PCIE_6A QCOM_ICC_TAG_ALWAYS

					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,

					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS

					 &cnoc_main SLAVE_PCIE_6A QCOM_ICC_TAG_ALWAYS>;

			interconnect-names = "pcie-mem",

					     "cpu-pcie";



			resets = <&gcc GCC_PCIE_6A_BCR>,

				 <&gcc GCC_PCIE_6A_LINK_DOWN_BCR>;

			reset-names = "pci",

				      "link_down";



			power-domains = <&gcc GCC_PCIE_6A_GDSC>;



			phys = <&pcie6a_phy>;

			phy-names = "pciephy";



			status = "disabled";

		};



		pcie6a_phy: phy@1bfc000 {

			compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy";

			reg = <0 0x01bfc000 0 0x2000>;



			clocks = <&gcc GCC_PCIE_6A_PHY_AUX_CLK>,

				 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>,

				 <&rpmhcc RPMH_CXO_CLK>,

				 <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>,

				 <&gcc GCC_PCIE_6A_PIPE_CLK>;

			clock-names = "aux",

				      "cfg_ahb",

				      "ref",

				      "rchng",

				      "pipe";



			resets = <&gcc GCC_PCIE_6A_PHY_BCR>,

				 <&gcc GCC_PCIE_6A_NOCSR_COM_PHY_BCR>;

			reset-names = "phy",

				      "phy_nocsr";



			assigned-clocks = <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>;

			assigned-clock-rates = <100000000>;



			power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>;



			#clock-cells = <0>;

			clock-output-names = "pcie6a_pipe_clk";



			#phy-cells = <0>;



			status = "disabled";

		};



		pcie4: pci@1c08000 {

			device_type = "pci";

			compatible = "qcom,pcie-x1e80100";

			reg = <0 0x01c08000 0 0x3000>,

			      <0 0x7c000000 0 0xf1d>,

			      <0 0x7c000f40 0 0xa8>,

			      <0 0x7c001000 0 0x1000>,

			      <0 0x7c100000 0 0x100000>,

			      <0 0x01c0b000 0 0x1000>;

			reg-names = "parf",

			            "dbi",

				    "elbi",

				    "atu",

				    "config",

				    "mhi";

			#address-cells = <3>;

			#size-cells = <2>;

			ranges = <0x01000000 0 0x00000000 0 0x7c200000 0 0x100000>,

				 <0x02000000 0 0x7c300000 0 0x7c300000 0 0x3d00000>;

			bus-range = <0x00 0xff>;



			dma-coherent;



			linux,pci-domain = <5>;

			num-lanes = <2>;



			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "msi0",

					  "msi1",

					  "msi2",

					  "msi3",

					  "msi4",

					  "msi5",

					  "msi6",

					  "msi7";



			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 0x7>;

			interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,

					<0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>,

					<0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>,

					<0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>;



			clocks = <&gcc GCC_PCIE_4_AUX_CLK>,

				 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,

				 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>,

				 <&gcc GCC_PCIE_4_SLV_AXI_CLK>,

				 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,

				 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>,

				 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>;

			clock-names = "aux",

				      "cfg",

				      "bus_master",

				      "bus_slave",

				      "slave_q2a",

				      "noc_aggr",

				      "cnoc_sf_axi";



			assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;

			assigned-clock-rates = <19200000>;



			interconnects = <&pcie_south_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS

					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,

					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS

					 &cnoc_main SLAVE_PCIE_4 QCOM_ICC_TAG_ALWAYS>;

			interconnect-names = "pcie-mem",

					     "cpu-pcie";



			resets = <&gcc GCC_PCIE_4_BCR>,

				 <&gcc GCC_PCIE_4_LINK_DOWN_BCR>;

			reset-names = "pci",

				      "link_down";



			power-domains = <&gcc GCC_PCIE_4_GDSC>;



			phys = <&pcie4_phy>;

			phy-names = "pciephy";



			status = "disabled";

		};



		pcie4_phy: phy@1c0e000 {

			compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy";

			reg = <0 0x01c0e000 0 0x2000>;



			clocks = <&gcc GCC_PCIE_4_AUX_CLK>,

				 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,

				 <&rpmhcc RPMH_CXO_CLK>,

				 <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>,

				 <&gcc GCC_PCIE_4_PIPE_CLK>;

			clock-names = "aux",

				      "cfg_ahb",

				      "ref",

				      "rchng",

				      "pipe";



			resets = <&gcc GCC_PCIE_4_PHY_BCR>;

			reset-names = "phy";



			assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>;

			assigned-clock-rates = <100000000>;



			power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>;



			#clock-cells = <0>;

			clock-output-names = "pcie4_pipe_clk";



			#phy-cells = <0>;



			status = "disabled";

		};



		tcsr_mutex: hwlock@1f40000 {

			compatible = "qcom,tcsr-mutex";

			reg = <0 0x01f40000 0 0x20000>;