Unverified Commit 5fac6c27 authored by Mark Brown's avatar Mark Brown
Browse files

Add STM32MP25 SPI NOR support 

Merge series from patrice.chotard@foss.st.com:

This series adds SPI NOR support for STM32MP25 SoCs from STMicroelectronics.

On STM32MP25 SoCs family, an Octo Memory Manager block manages the muxing,
the memory area split, the chip select override and the time constraint
between its 2 Octo SPI children.

Due to these depedencies, this series adds support for:
  - Octo Memory Manager driver (not applied for SPI).
  - Octo SPI driver.
  - yaml schema for Octo Memory Manager and Octo SPI drivers.

The device tree files adds Octo Memory Manager and its 2 associated Octo
SPI chidren in stm32mp251.dtsi and adds SPI NOR support in stm32mp257f-ev1
board.
parents 7304d190 79b8a705

.mailmap

+1 −0
Original line number Diff line number Diff line
@@ -376,6 +376,7 @@ Juha Yrjola <juha.yrjola@solidboot.com> 
Julien Thierry <julien.thierry.kdev@gmail.com> <julien.thierry@arm.com>

Iskren Chernev <me@iskren.info> <iskren.chernev@gmail.com>

Kalle Valo <kvalo@kernel.org> <kvalo@codeaurora.org>

Kalle Valo <kvalo@kernel.org> <quic_kvalo@quicinc.com>

Kalyan Thota <quic_kalyant@quicinc.com> <kalyan_t@codeaurora.org>

Karthikeyan Periyasamy <quic_periyasa@quicinc.com> <periyasa@codeaurora.org>

Kathiravan T <quic_kathirav@quicinc.com> <kathirav@codeaurora.org>

CREDITS

+2 −4
Original line number Diff line number Diff line
@@ -2515,11 +2515,9 @@ D: SLS distribution 
D: Initial implementation of VC's, pty's and select()



N: Pavel Machek

E: pavel@ucw.cz

E: pavel@kernel.org

P: 4096R/92DFCE96 4FA7 9EEF FCD4 C44F C585  B8C7 C060 2241 92DF CE96

D: Softcursor for vga, hypertech cdrom support, vcsa bugfix, nbd,

D: sun4/330 port, capabilities for elf, speedup for rm on ext2, USB,

D: work on suspend-to-ram/disk, killing duplicates from ioctl32,

D: NBD, Sun4/330 port, USB, work on suspend-to-ram/disk,

D: Altera SoCFPGA and Nokia N900 support.

S: Czech Republic

Documentation/arch/arm64/gcs.rst

+1 −1
Original line number Diff line number Diff line
@@ -37,7 +37,7 @@ intended to be exhaustive. 
  shadow stacks rather than GCS.



* Support for GCS is reported to userspace via HWCAP_GCS in the aux vector

  AT_HWCAP2 entry.

  AT_HWCAP entry.



* GCS is enabled per thread.  While there is support for disabling GCS

  at runtime this should be done with great care.

Documentation/devicetree/bindings/clock/qcom,gpucc.yaml

+3 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ title: Qualcomm Graphics Clock & Reset Controller 


maintainers:

  - Taniya Das <quic_tdas@quicinc.com>

  - Imran Shaik <quic_imrashai@quicinc.com>



description: |

  Qualcomm graphics clock control module provides the clocks, resets and power
@@ -23,10 +24,12 @@ description: | 
    include/dt-bindings/clock/qcom,gpucc-sm8150.h

    include/dt-bindings/clock/qcom,gpucc-sm8250.h

    include/dt-bindings/clock/qcom,gpucc-sm8350.h

    include/dt-bindings/clock/qcom,qcs8300-gpucc.h



properties:

  compatible:

    enum:

      - qcom,qcs8300-gpucc

      - qcom,sdm845-gpucc

      - qcom,sa8775p-gpucc

      - qcom,sc7180-gpucc

Documentation/devicetree/bindings/clock/qcom,sa8775p-camcc.yaml

+5 −1
Original line number Diff line number Diff line
@@ -8,16 +8,20 @@ title: Qualcomm Camera Clock & Reset Controller on SA8775P 


maintainers:

  - Taniya Das <quic_tdas@quicinc.com>

  - Imran Shaik <quic_imrashai@quicinc.com>



description: |

  Qualcomm camera clock control module provides the clocks, resets and power

  domains on SA8775p.



  See also: include/dt-bindings/clock/qcom,sa8775p-camcc.h

  See also:

    include/dt-bindings/clock/qcom,qcs8300-camcc.h

    include/dt-bindings/clock/qcom,sa8775p-camcc.h



properties:

  compatible:

    enum:

      - qcom,qcs8300-camcc

      - qcom,sa8775p-camcc



  clocks: