Commit 5fb02493 authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull pin control updates from Linus Walleij:
 "We have GPIO awareness in the pin control core and an interesting
  AAEON driver.

  Core changes:

   - Allow pins to be identified/marked as GPIO mode with a special
     callback.

     The pin controller core is now "aware" if a pin is in GPIO mode if
     the callback is implemented in the driver, and can thus be marked
     as "strict", i.e. disallowing simultaneous use of a line as GPIO
     and another function such as I2C.

     This is enabled in the Qualcomm TLMM driver and also implemeted
     from day 1 in the new Broadcom STB driver

   - Rename the pin config option PIN_CONFIG_OUTPUT to PIN_CONFIG_LEVEL
     to better describe what the config is doing, as well as making it
     more intuitive what shall be returned when reading this property

  New drivers:

   - Qualcomm SDM660 LPASS LPI TLMM pin controller subdriver

   - Qualcomm Glymur family pin controller driver

   - Broadcom STB family pin controller driver

   - Tegra186 pin controller driver

   - AAEON UP pin controller support.

     This is some special pin controller that works as an external
     advanced line MUX and amplifier for signals from an Intel SoC. A
     cooperative effort with the GPIO maintainer was needed to reach a
     solution where we reuse code from the GPIO aggregator/forwarder
     driver

   - Renesas RZ/T2H and RZ/N2H pin controller support

   - Axis ARTPEC-8 subdriver for the Samsung pin controller driver

  Improvements:

   - Output enable (OEN) support in the Renesas RZG2L driver

   - Properly support bias pull up/down in the pinctrl-single driver

   - Move over all GPIO portions using generic MMIO GPIO to the new
     generic GPIO chip management which has a nice and separate API

   - Proper DT bindings for some older Broadcom SoCs

   - External GPIO (EGPIO) support in the Qualcomm SM8250

  Deleted code:

   - Dropped the now unused Samsung S3C24xx drivers"

* tag 'pinctrl-v6.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (75 commits)
  pinctrl: use more common syntax for compound literals
  pinctrl: Simplify printks with pOF format
  pinctrl: qcom: Add SDM660 LPASS LPI TLMM
  dt-bindings: pinctrl: qcom: Add SDM660 LPI pinctrl
  pinctrl: qcom: lpass-lpi: Add ability to use custom pin offsets
  pinctrl: qcom: Add glymur pinctrl driver
  dt-bindings: pinctrl: qcom: Add Glymur pinctrl
  pinctrl: qcom: sm8250: Add egpio support
  pinctrl: generic: rename PIN_CONFIG_OUTPUT to LEVEL
  pinctrl: keembay: fix double free in keembay_build_functions()
  pinctrl: spacemit: fix typo in PRI_TDI pin name
  pinctrl: eswin: Fix regulator error check and Kconfig dependency
  pinctrl: bcm: Add STB family pin controller driver
  dt-bindings: pinctrl: Add support for Broadcom STB pin controller
  pinctrl: qcom: make the pinmuxing strict
  pinctrl: qcom: mark the `gpio` and `egpio` pins function as non-strict functions
  pinctrl: qcom: add infrastructure for marking pin functions as GPIOs
  pinctrl: allow to mark pin functions as requestable GPIOs
  pinctrl: qcom: use generic pin function helpers
  pinctrl: make struct pinfunction a pointer in struct function_desc
  ...
parents 524c4a5d da3a88e9
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/brcm,bcm2712c0-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom STB family pin controller

maintainers:
  - Ivan T. Ivanov <iivanov@suse.de>
  - A. della Porta <andrea.porta@suse.com>

description: >
  Broadcom's STB family of memory-mapped pin controllers.

  This includes the pin controllers inside the BCM2712 SoC which
  are instances of the STB family and has two silicon variants,
  C0 and D0, which differs slightly in terms of registers layout.

  The -aon- (Always On) variant is the same IP block but differs
  in the number of pins that are associated and the pinmux functions
  for each of those pins.

allOf:
  - $ref: pinctrl.yaml#

properties:
  compatible:
    enum:
      - brcm,bcm2712c0-pinctrl
      - brcm,bcm2712c0-aon-pinctrl
      - brcm,bcm2712d0-pinctrl
      - brcm,bcm2712d0-aon-pinctrl

  reg:
    maxItems: 1

patternProperties:
  '-state$':
    oneOf:
      - $ref: '#/$defs/brcmstb-pinctrl-state'
      - patternProperties:
          '-pins$':
            $ref: '#/$defs/brcmstb-pinctrl-state'
        additionalProperties: false

$defs:
  brcmstb-pinctrl-state:
    allOf:
      - $ref: pincfg-node.yaml#
      - $ref: pinmux-node.yaml#

    description: >
      Pin controller client devices use pin configuration subnodes (children
      and grandchildren) for desired pin configuration.

      Client device subnodes use below standard properties.

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode (either this or "groups" must be specified).
        items:
          pattern: '^((aon_)?s?gpio[0-6]?[0-9])|(emmc_(clk|cmd|dat[0-7]|ds))$'

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins.
        enum: [ gpio, alt1, alt2, alt3, alt4, alt5, alt6, alt7, alt8,
                aon_cpu_standbyb, aon_fp_4sec_resetb, aon_gpclk, aon_pwm,
                arm_jtag, aud_fs_clk0, avs_pmu_bsc, bsc_m0, bsc_m1, bsc_m2,
                bsc_m3, clk_observe, ctl_hdmi_5v, enet0, enet0_mii, enet0_rgmii,
                ext_sc_clk, fl0, fl1, gpclk0, gpclk1, gpclk2, hdmi_tx0_auto_i2c,
                hdmi_tx0_bsc, hdmi_tx1_auto_i2c, hdmi_tx1_bsc, i2s_in, i2s_out,
                ir_in, mtsif, mtsif_alt, mtsif_alt1, pdm, pkt, pm_led_out, sc0,
                sd0, sd2, sd_card_a, sd_card_b, sd_card_c, sd_card_d, sd_card_e,
                sd_card_f, sd_card_g, spdif_out, spi_m, spi_s, sr_edm_sense, te0,
                te1, tsio, uart0, uart1, uart2, usb_pwr, usb_vbus, uui, vc_i2c0,
                vc_i2c3, vc_i2c4, vc_i2c5, vc_i2csl, vc_pcm, vc_pwm0, vc_pwm1,
                vc_spi0, vc_spi3, vc_spi4, vc_spi5, vc_uart0, vc_uart2, vc_uart3,
                vc_uart4 ]

      bias-disable: true
      bias-pull-down: true
      bias-pull-up: true

    required:
      - pins

    if:
      properties:
        pins:
          not:
            contains:
              pattern: "^emmc_(clk|cmd|dat[0-7]|ds)$"
    then:
      required:
        - function
    else:
      properties:
        function: false

    additionalProperties: false

required:
  - compatible
  - reg

unevaluatedProperties: false

examples:
  - |
    pinctrl@7d504100 {
        compatible = "brcm,bcm2712c0-pinctrl";
        reg = <0x7d504100 0x30>;

        bt-shutdown-default-state {
            function = "gpio";
            pins = "gpio29";
        };

        uarta-default-state {
            rts-tx-pins {
                function = "uart0";
                pins = "gpio24", "gpio26";
                bias-disable;
            };

            cts-rx-pins {
                function = "uart0";
                pins = "gpio25", "gpio27";
                bias-pull-up;
            };
        };
    };
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Broadcom BCM2835 GPIO (and pinmux) controller

The BCM2835 GPIO module is a combined GPIO controller, (GPIO) interrupt
controller, and pinmux/control device.

Required properties:
- compatible: "brcm,bcm2835-gpio"
- compatible: should be one of:
  "brcm,bcm2835-gpio" - BCM2835 compatible pinctrl
  "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
  "brcm,bcm2711-gpio" - BCM2711 compatible pinctrl
  "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
- reg: Should contain the physical address of the GPIO module's registers.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells : Should be two. The first cell is the pin number and the
  second cell is used to specify optional parameters:
  - bit 0 specifies polarity (0 for normal, 1 for inverted)
- interrupts : The interrupt outputs from the controller. One interrupt per
  individual bank followed by the "all banks" interrupt. For BCM7211, an
  additional set of per-bank interrupt line and an "all banks" wake-up
  interrupt may be specified.
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells : Should be 2.
  The first cell is the GPIO number.
  The second cell is used to specify flags:
    bits[3:0] trigger type and level flags:
      1 = low-to-high edge triggered.
      2 = high-to-low edge triggered.
      4 = active high level-sensitive.
      8 = active low level-sensitive.
    Valid combinations are 1, 2, 3, 4, 8.

Please refer to ../gpio/gpio.txt for a general description of GPIO bindings.

Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".

Each pin configuration node lists the pin(s) to which it applies, and one or
more of the mux function to select on those pin(s), and pull-up/down
configuration. Each subnode only affects those parameters that are explicitly
listed. In other words, a subnode that lists only a mux function implies no
information about any pull configuration. Similarly, a subnode that lists only
a pul parameter implies no information about the mux function.

The BCM2835 pin configuration and multiplexing supports the generic bindings.
For details on each properties, you can refer to ./pinctrl-bindings.txt.

Required sub-node properties:
  - pins
  - function

Optional sub-node properties:
  - bias-disable
  - bias-pull-up
  - bias-pull-down
  - output-high
  - output-low

Legacy pin configuration and multiplexing binding:
*** (Its use is deprecated, use generic multiplexing and configuration
bindings instead)

Required subnode-properties:
- brcm,pins: An array of cells. Each cell contains the ID of a pin. Valid IDs
  are the integer GPIO IDs; 0==GPIO0, 1==GPIO1, ... 53==GPIO53.

Optional subnode-properties:
- brcm,function: Integer, containing the function to mux to the pin(s):
  0: GPIO in
  1: GPIO out
  2: alt5
  3: alt4
  4: alt0
  5: alt1
  6: alt2
  7: alt3
- brcm,pull: Integer, representing the pull-down/up to apply to the pin(s):
  0: none
  1: down
  2: up

Each of brcm,function and brcm,pull may contain either a single value which
will be applied to all pins in brcm,pins, or 1 value for each entry in
brcm,pins.

Example:

	gpio: gpio {
		compatible = "brcm,bcm2835-gpio";
		reg = <0x2200000 0xb4>;
		interrupts = <2 17>, <2 19>, <2 18>, <2 20>;

		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/brcm,bcm2835-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom BCM2835 GPIO (and pinmux) controller

maintainers:
  - Florian Fainelli <f.fainelli@gmail.com>

description: >
  The BCM2835 GPIO module is a combined GPIO controller, (GPIO) interrupt
  controller, and pinmux/control device.

properties:
  compatible:
    enum:
      - brcm,bcm2835-gpio
      - brcm,bcm2711-gpio
      - brcm,bcm7211-gpio

  reg:
    maxItems: 1

  '#gpio-cells':
    const: 2

  gpio-controller: true
  gpio-ranges: true
  gpio-line-names: true

  interrupts:
    description: >
      Interrupt outputs: one per bank, then the combined “all banks” line.
      BCM7211 may specify up to four per-bank wake-up lines and one combined
      wake-up interrupt.
    minItems: 4
    maxItems: 10

  '#interrupt-cells':
    const: 2

  interrupt-controller: true

additionalProperties:
  oneOf:
    - type: object
      additionalProperties: false

      patternProperties:
        '^pins?-':
          type: object
          allOf:
            - $ref: /schemas/pinctrl/pincfg-node.yaml#
            - $ref: /schemas/pinctrl/pinmux-node.yaml#
          additionalProperties: false

          properties:
            pins: true
            function: true
            bias-disable: true
            bias-pull-up: true
            bias-pull-down: true
            output-high: true
            output-low: true

          required:
            - pins
            - function

    - type: object
      additionalProperties: false
      deprecated: true

      properties:
        brcm,pins:
          description:
            GPIO pin numbers for legacy configuration.
          $ref: /schemas/types.yaml#/definitions/uint32-array

        brcm,function:
          description:
            Legacy mux function for the pins (0=input, 1=output, 2–7=alt functions).
          $ref: /schemas/types.yaml#/definitions/uint32-array
          maximum: 7

        brcm,pull:
          description: >
            Legacy pull setting for the pins (0=none, 1=pull-down, 2=pull-up).
          $ref: /schemas/types.yaml#/definitions/uint32-array
          maximum: 2

      required:
        - brcm,pins

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - brcm,bcm2835-gpio
              - brcm,bcm2711-gpio
    then:
      properties:
        interrupts:
          maxItems: 5

examples:
  - |
    gpio@2200000 {
        compatible = "brcm,bcm2835-gpio";
        reg = <0x2200000 0xb4>;
        interrupts = <2 17>, <2 19>, <2 18>, <2 20>, <2 21>;
        #gpio-cells = <2>;
        gpio-controller;
        #interrupt-cells = <2>;
        interrupt-controller;
    };
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Broadcom iProc GPIO/PINCONF Controller

Required properties:

- compatible:
    "brcm,iproc-gpio" for the generic iProc based GPIO controller IP that
    supports full-featured pinctrl and GPIO functions used in various iProc
    based SoCs

    May contain an SoC-specific compatibility string to accommodate any
    SoC-specific features

    "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or
    "brcm,cygnus-crmu-gpio" for Cygnus SoCs

    "brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support
    disabled

    "brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general
    pinctrl support completely disabled in this IP block. In Stingray, a
    different IP block is used to handle pinctrl related functions

- reg:
    Define the base and range of the I/O address space that contains SoC
GPIO/PINCONF controller registers

- ngpios:
    Total number of in-use slots in GPIO controller

- #gpio-cells:
    Must be two. The first cell is the GPIO pin number (within the
controller's pin space) and the second cell is used for the following:
    bit[0]: polarity (0 for active high and 1 for active low)

- gpio-controller:
    Specifies that the node is a GPIO controller

Optional properties:

- interrupts:
    Interrupt ID

- interrupt-controller:
    Specifies that the node is an interrupt controller

- gpio-ranges:
    Specifies the mapping between gpio controller and pin-controllers pins.
    This requires 4 fields in cells defined as -
    1. Phandle of pin-controller.
    2. GPIO base pin offset.
    3  Pin-control base pin offset.
    4. number of gpio pins which are linearly mapped from pin base.

Supported generic PINCONF properties in child nodes:

- pins:
    The list of pins (within the controller's own pin space) that properties
in the node apply to. Pin names are "gpio-<pin>"

- bias-disable:
    Disable pin bias

- bias-pull-up:
    Enable internal pull up resistor

- bias-pull-down:
    Enable internal pull down resistor

- drive-strength:
    Valid drive strength values include 2, 4, 6, 8, 10, 12, 14, 16 (mA)

Example:
	gpio_ccm: gpio@1800a000 {
		compatible = "brcm,cygnus-ccm-gpio";
		reg = <0x1800a000 0x50>,
		      <0x0301d164 0x20>;
		ngpios = <24>;
		#gpio-cells = <2>;
		gpio-controller;
		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-controller;

		touch_pins: touch_pins {
			pwr: pwr {
				pins = "gpio-0";
				drive-strength = <16>;
			};

			event: event {
				pins = "gpio-1";
				bias-pull-up;
			};
		};
	};

	gpio_asiu: gpio@180a5000 {
		compatible = "brcm,cygnus-asiu-gpio";
		reg = <0x180a5000 0x668>;
		ngpios = <146>;
		#gpio-cells = <2>;
		gpio-controller;
		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-controller;
		gpio-ranges = <&pinctrl 0 42 1>,
				<&pinctrl 1 44 3>;
	};

	/*
	 * Touchscreen that uses the CCM GPIO 0 and 1
	 */
	tsc {
		...
		...
		gpio-pwr = <&gpio_ccm 0 0>;
		gpio-event = <&gpio_ccm 1 0>;
	};

	/* Bluetooth that uses the ASIU GPIO 5, with polarity inverted */
	bluetooth {
		...
		...
		bcm,rfkill-bank-sel = <&gpio_asiu 5 1>
	}
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/brcm,iproc-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom iProc GPIO/PINCONF Controller

maintainers:
  - Ray Jui <rjui@broadcom.com>
  - Scott Branden <sbranden@broadcom.com>

properties:
  compatible:
    oneOf:
      - enum:
          - brcm,cygnus-asiu-gpio
          - brcm,cygnus-ccm-gpio
          - brcm,cygnus-crmu-gpio
          - brcm,iproc-gpio
          - brcm,iproc-stingray-gpio
      - items:
          - enum:
              - brcm,iproc-hr2-gpio
              - brcm,iproc-nsp-gpio
          - const: brcm,iproc-gpio

  reg:
    minItems: 1
    items:
      - description: GPIO Bank registers
      - description: IO Ctrl registers

  "#gpio-cells":
    const: 2

  gpio-controller: true

  gpio-ranges: true

  ngpios: true

  "#interrupt-cells":
    const: 2

  interrupts:
    maxItems: 1

  interrupt-controller: true

required:
  - compatible
  - reg
  - "#gpio-cells"
  - gpio-controller
  - ngpios

patternProperties:
  '-pins$':
    type: object
    additionalProperties:
      description: Pin configuration child nodes.
      allOf:
        - $ref: pincfg-node.yaml#
        - $ref: pinmux-node.yaml#
      additionalProperties: false

      properties:
        pins:
          items:
            pattern: '^gpio-'

        bias-disable: true
        bias-pull-up: true
        bias-pull-down: true

        drive-strength:
          enum: [ 2, 4, 6, 8, 10, 12, 14, 16 ]

      required:
        - pins

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    gpio@1800a000 {
        compatible = "brcm,cygnus-ccm-gpio";
        reg = <0x1800a000 0x50>,
              <0x0301d164 0x20>;
        ngpios = <24>;
        #gpio-cells = <2>;
        gpio-controller;
        #interrupt-cells = <2>;
        interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-controller;

        touch-pins {
            pwr {
                pins = "gpio-0";
                drive-strength = <16>;
            };

            event {
                pins = "gpio-1";
                bias-pull-up;
            };
        };
    };
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