Commit 6068bc20 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/dsi: pass display to register macros instead of implicit variable 



Stop relying on the dev_priv local variable in the DSI register
macros. Pass struct intel_display pointer to the macros. Move the MIPI
DSI MMIO base selection to a different level, passing it to _MMIO_MIPI()
and doing the addition there.

Start using the local display variable for all intel_de_* usage, and
opportunistically use it for other things than display registers as
well.

Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/6dd52f3fce3527242479aadc276d05de74ceae5d.1713520813.git.jani.nikula@intel.com


Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 4cfff967

drivers/gpu/drm/i915/display/intel_display.c

+4 −4
Original line number Diff line number Diff line
@@ -3722,8 +3722,8 @@ static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, 
					 struct intel_crtc_state *pipe_config,

					 struct intel_display_power_domain_set *power_domain_set)

{

	struct drm_device *dev = crtc->base.dev;

	struct drm_i915_private *dev_priv = to_i915(dev);

	struct intel_display *display = to_intel_display(crtc);

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	enum transcoder cpu_transcoder;

	enum port port;

	u32 tmp;
@@ -3749,11 +3749,11 @@ static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, 
			break;



		/* XXX: this works for video mode only */

		tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port));

		tmp = intel_de_read(display, BXT_MIPI_PORT_CTRL(port));

		if (!(tmp & DPI_ENABLE))

			continue;



		tmp = intel_de_read(dev_priv, MIPI_CTRL(port));

		tmp = intel_de_read(display, MIPI_CTRL(display, port));

		if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))

			continue;

drivers/gpu/drm/i915/display/vlv_dsi.c

+174 −163

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

+11 −11
Original line number Diff line number Diff line
@@ -365,13 +365,13 @@ u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, 


void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)

{

	u32 temp;

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_display *display = to_intel_display(encoder);

	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);

	u32 temp;



	temp = intel_de_read(dev_priv, MIPI_CTRL(port));

	temp = intel_de_read(display, MIPI_CTRL(display, port));

	temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;

	intel_de_write(dev_priv, MIPI_CTRL(port),

	intel_de_write(display, MIPI_CTRL(display, port),

		       temp | intel_dsi->escape_clk_div << ESCAPE_CLOCK_DIVIDER_SHIFT);

}
@@ -570,24 +570,24 @@ void bxt_dsi_pll_enable(struct intel_encoder *encoder, 


void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)

{

	struct intel_display *display = to_intel_display(encoder);

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	u32 tmp;

	struct drm_device *dev = encoder->base.dev;

	struct drm_i915_private *dev_priv = to_i915(dev);



	/* Clear old configurations */

	if (IS_BROXTON(dev_priv)) {

		tmp = intel_de_read(dev_priv, BXT_MIPI_CLOCK_CTL);

		tmp = intel_de_read(display, BXT_MIPI_CLOCK_CTL);

		tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));

		tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));

		tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));

		tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));

		intel_de_write(dev_priv, BXT_MIPI_CLOCK_CTL, tmp);

		intel_de_write(display, BXT_MIPI_CLOCK_CTL, tmp);

	} else {

		intel_de_rmw(dev_priv, MIPIO_TXESC_CLK_DIV1, GLK_TX_ESC_CLK_DIV1_MASK, 0);

		intel_de_rmw(display, MIPIO_TXESC_CLK_DIV1, GLK_TX_ESC_CLK_DIV1_MASK, 0);



		intel_de_rmw(dev_priv, MIPIO_TXESC_CLK_DIV2, GLK_TX_ESC_CLK_DIV2_MASK, 0);

		intel_de_rmw(display, MIPIO_TXESC_CLK_DIV2, GLK_TX_ESC_CLK_DIV2_MASK, 0);

	}

	intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP);

	intel_de_write(display, MIPI_EOT_DISABLE(display, port), CLOCKSTOP);

}



static void assert_dsi_pll(struct drm_i915_private *i915, bool state)

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

+160 −164

File changed.

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