Commit 613f3255 authored by Inochi Amaoto's avatar Inochi Amaoto Committed by Manivannan Sadhasivam
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PCI: sophgo: Disable L0s and L1 on Sophgo 2044 PCIe Root Ports 



Sophgo 2044 Root Ports advertise L0 and L1 capabilities without supporting
them. Since commit f3ac2ff1 ("PCI/ASPM: Enable all ClockPM and ASPM
states for devicetree platforms") force enabled ASPM on all device tree
platforms, the issue became evident and the SG2044 Root Port started
breaking.

Hence, disable the L0s and L1 capabilities in the LINKCAP register for the
SG2044 Root Ports, so that these states won't get enabled.

Fixes: 467d9c03 ("PCI: dwc: Add Sophgo SG2044 PCIe controller driver in Root Complex mode")
Signed-off-by: default avatarInochi Amaoto <inochiama@gmail.com>
[mani: reworded description and corrected fixes tag]
Signed-off-by: default avatarManivannan Sadhasivam <mani@kernel.org>
Tested-by: default avatarHan Gao <gaohan@iscas.ac.cn>
Link: https://patch.msgid.link/20260109040756.731169-1-inochiama@gmail.com
parent 8f0b4cce

drivers/pci/controller/dwc/pcie-sophgo.c

+18 −0
Original line number Diff line number Diff line
@@ -161,6 +161,22 @@ static void sophgo_pcie_msi_enable(struct dw_pcie_rp *pp) 
	raw_spin_unlock_irqrestore(&pp->lock, flags);

}



static void sophgo_pcie_disable_l0s_l1(struct dw_pcie_rp *pp)

{

	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);

	u32 offset, val;



	offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);



	dw_pcie_dbi_ro_wr_en(pci);



	val = dw_pcie_readl_dbi(pci, PCI_EXP_LNKCAP + offset);

	val &= ~(PCI_EXP_LNKCAP_ASPM_L0S | PCI_EXP_LNKCAP_ASPM_L1);

	dw_pcie_writel_dbi(pci, PCI_EXP_LNKCAP + offset, val);



	dw_pcie_dbi_ro_wr_dis(pci);

}



static int sophgo_pcie_host_init(struct dw_pcie_rp *pp)

{

	int irq;
@@ -171,6 +187,8 @@ static int sophgo_pcie_host_init(struct dw_pcie_rp *pp) 


	irq_set_chained_handler_and_data(irq, sophgo_pcie_intx_handler, pp);



	sophgo_pcie_disable_l0s_l1(pp);



	sophgo_pcie_msi_enable(pp);



	return 0;