Commit 615a292e authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Bjorn Andersson
Browse files

clk: qcom: dispcc-sm8650: fix DisplayPort clocks 



On SM8650 DisplayPort link clocks use frequency tables inherited from
the vendor kernel, it is not applicable in the upstream kernel. Drop
frequency tables and use clk_byte2_ops for those clocks.

This fixes frequency selection in the OPP core (which otherwise attempts
to use invalid 810 KHz as DP link rate), also fixing the following
message:
msm-dp-display af54000.displayport-controller: _opp_config_clk_single: failed to set clock rate: -22

Fixes: 9e939f00 ("clk: qcom: add the SM8650 Display Clock Controller driver")
Reviewed-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-HDK
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240424-dispcc-dp-clocks-v2-4-b44038f3fa96@linaro.org


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent e90b5139

drivers/clk/qcom/dispcc-sm8650.c

+4 −16
Original line number Diff line number Diff line
@@ -343,26 +343,17 @@ static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = { 
	},

};



static const struct freq_tbl ftbl_disp_cc_mdss_dptx0_link_clk_src[] = {

	F(162000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),

	F(270000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),

	F(540000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),

	F(810000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),

	{ }

};



static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = {

	.cmd_rcgr = 0x8170,

	.mnd_width = 0,

	.hid_width = 5,

	.parent_map = disp_cc_parent_map_7,

	.freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,

	.clkr.hw.init = &(const struct clk_init_data) {

		.name = "disp_cc_mdss_dptx0_link_clk_src",

		.parent_data = disp_cc_parent_data_7,

		.num_parents = ARRAY_SIZE(disp_cc_parent_data_7),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		.ops = &clk_byte2_ops,

	},

};
@@ -416,13 +407,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = { 
	.mnd_width = 0,

	.hid_width = 5,

	.parent_map = disp_cc_parent_map_3,

	.freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,

	.clkr.hw.init = &(const struct clk_init_data) {

		.name = "disp_cc_mdss_dptx1_link_clk_src",

		.parent_data = disp_cc_parent_data_3,

		.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		.ops = &clk_byte2_ops,

	},

};
@@ -476,13 +466,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = { 
	.mnd_width = 0,

	.hid_width = 5,

	.parent_map = disp_cc_parent_map_3,

	.freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,

	.clkr.hw.init = &(const struct clk_init_data) {

		.name = "disp_cc_mdss_dptx2_link_clk_src",

		.parent_data = disp_cc_parent_data_3,

		.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		.ops = &clk_byte2_ops,

	},

};
@@ -536,13 +525,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = { 
	.mnd_width = 0,

	.hid_width = 5,

	.parent_map = disp_cc_parent_map_3,

	.freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,

	.clkr.hw.init = &(const struct clk_init_data) {

		.name = "disp_cc_mdss_dptx3_link_clk_src",

		.parent_data = disp_cc_parent_data_3,

		.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		.ops = &clk_byte2_ops,

	},

};