Unverified Commit 61609bf2 authored by Yu Chien Peter Lin's avatar Yu Chien Peter Lin Committed by Palmer Dabbelt
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dt-bindings: riscv: Add Andes PMU extension description 



Document the ISA string for Andes Technology performance monitor
extension which provides counter overflow interrupt and mode
filtering mechanisms.

Signed-off-by: default avatarYu Chien Peter Lin <peterlin@andestech.com>
Acked-by: default avatarConor Dooley <conor.dooley@microchip.com>
Reviewed-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20240222083946.3977135-9-peterlin@andestech.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent bc969d6c

Documentation/devicetree/bindings/riscv/extensions.yaml

+7 −0
Original line number Diff line number Diff line
@@ -477,5 +477,12 @@ properties: 
            latency, as ratified in commit 56ed795 ("Update

            riscv-crypto-spec-vector.adoc") of riscv-crypto.



        - const: xandespmu

          description:

            The Andes Technology performance monitor extension for counter overflow

            and privilege mode filtering. For more details, see Counter Related

            Registers in the AX45MP datasheet.

            https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf



additionalProperties: true

...