Commit 6245237a authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Jakub Kicinski
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net: pcs: rzn1-miic: Make switch mode mask SoC-specific 



Move the hardcoded switch mode mask definition into the SoC-specific
miic_of_data structure. This allows each SoC to define its own mask
value rather than relying on a single fixed constant. For RZ/N1 the
mask remains GENMASK(4, 0).

This is in preparation for adding support for RZ/T2H, where the
switch mode mask is GENMASK(2, 0).

Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Tested-by: default avatarWolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://patch.msgid.link/20250910204132.319975-7-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent c112520d

drivers/net/pcs/pcs-rzn1-miic.c

+9 −2
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 


#include <linux/array_size.h>

#include <linux/bits.h>

#include <linux/bitops.h>

#include <linux/clk.h>

#include <linux/device.h>

#include <linux/mdio.h>
@@ -23,7 +24,6 @@ 
#define MIIC_ESID_CODE			0x4



#define MIIC_MODCTRL			0x8

#define MIIC_MODCTRL_SW_MODE		GENMASK(4, 0)



#define MIIC_CONVCTRL(port)		(0x100 + (port) * 4)
@@ -146,6 +146,7 @@ struct miic { 
 * @index_to_string_count: Number of entries in the index_to_string array

 * @miic_port_start: MIIC port start number

 * @miic_port_max: Maximum MIIC supported

 * @sw_mode_mask: Switch mode mask

 */

struct miic_of_data {

	struct modctrl_match *match_table;
@@ -157,6 +158,7 @@ struct miic_of_data { 
	u8 index_to_string_count;

	u8 miic_port_start;

	u8 miic_port_max;

	u8 sw_mode_mask;

};



/**
@@ -402,6 +404,7 @@ EXPORT_SYMBOL(miic_destroy); 


static int miic_init_hw(struct miic *miic, u32 cfg_mode)

{

	u8 sw_mode_mask = miic->of_data->sw_mode_mask;

	int port;



	/* Unlock write access to accessory registers (cf datasheet). If this
@@ -413,8 +416,11 @@ static int miic_init_hw(struct miic *miic, u32 cfg_mode) 
	miic_reg_writel(miic, MIIC_PRCMD, 0xFFFE);

	miic_reg_writel(miic, MIIC_PRCMD, 0x0001);



	/* TODO: Replace with FIELD_PREP() when compile-time constant

	 * restriction is lifted. Currently __ffs() returns 0 for sw_mode_mask.

	 */

	miic_reg_writel(miic, MIIC_MODCTRL,

			FIELD_PREP(MIIC_MODCTRL_SW_MODE, cfg_mode));

			((cfg_mode << __ffs(sw_mode_mask)) & sw_mode_mask));



	for (port = 0; port < miic->of_data->miic_port_max; port++) {

		miic_converter_enable(miic, port, 0);
@@ -582,6 +588,7 @@ static struct miic_of_data rzn1_miic_of_data = { 
	.index_to_string_count = ARRAY_SIZE(index_to_string),

	.miic_port_start = 1,

	.miic_port_max = 5,

	.sw_mode_mask = GENMASK(4, 0),

};



static const struct of_device_id miic_of_mtable[] = {