Commit 62e5a7e2 authored by Nicholas Kazlauskas's avatar Nicholas Kazlauskas Committed by Alex Deucher
Browse files

drm/amd/display: Fix surface optimization regression on Carrizo 



[Why]
DCE legacy optimization path isn't well tested under new DC optimization
flow which can result in underflow occuring when initializing X11 on
Carrizo.

[How]
Retain the legacy optimization flow for DCE and keep the new one for DCN
to satisfy optimizations being correctly applied for ASIC that can
support it.

Fixes: 34316c1e ("drm/amd/display: Optimize bandwidth on following fast update")
Reported-by: default avatarTom St Denis <tom.stdenis@amd.com>
Tested-by: default avatarTom St Denis <tom.stdenis@amd.com>
Reviewed-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9470620e

drivers/gpu/drm/amd/display/dc/core/dc.c

+13 −2
Original line number Diff line number Diff line
@@ -3118,8 +3118,13 @@ void dc_commit_updates_for_stream(struct dc *dc, 
			if (new_pipe->plane_state && new_pipe->plane_state != old_pipe->plane_state)

				new_pipe->plane_state->force_full_update = true;

		}

	} else if (update_type == UPDATE_TYPE_FAST) {

		/* Previous frame finished and HW is ready for optimization. */

	} else if (update_type == UPDATE_TYPE_FAST && dc_ctx->dce_version >= DCE_VERSION_MAX) {

		/*

		 * Previous frame finished and HW is ready for optimization.

		 *

		 * Only relevant for DCN behavior where we can guarantee the optimization

		 * is safe to apply - retain the legacy behavior for DCE.

		 */

		dc_post_update_surfaces_to_stream(dc);

	}
@@ -3178,6 +3183,12 @@ void dc_commit_updates_for_stream(struct dc *dc, 
		}

	}



	/* Legacy optimization path for DCE. */

	if (update_type >= UPDATE_TYPE_FULL && dc_ctx->dce_version < DCE_VERSION_MAX) {

		dc_post_update_surfaces_to_stream(dc);

		TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);

	}



	return;



}