Commit 63796bc2 authored by Pawel Dembicki's avatar Pawel Dembicki Committed by David S. Miller
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net: dsa: vsc73xx: fix port MAC configuration in full duplex mode 



According to the datasheet description ("Port Mode Procedure" in 5.6.2),
the VSC73XX_MAC_CFG_WEXC_DIS bit is configured only for half duplex mode.

The WEXC_DIS bit is responsible for MAC behavior after an excessive
collision. Let's set it as described in the datasheet.

Fixes: 05bd97fc ("net: dsa: Add Vitesse VSC73xx DSA router driver")
Reviewed-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Reviewed-by: default avatarFlorian Fainelli <florian.fainelli@broadcom.com>
Signed-off-by: default avatarPawel Dembicki <paweldembicki@gmail.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 9ff2f816

drivers/net/dsa/vitesse-vsc73xx-core.c

+5 −1
Original line number Diff line number Diff line
@@ -957,6 +957,11 @@ static void vsc73xx_mac_link_up(struct phylink_config *config, 


	if (duplex == DUPLEX_FULL)

		val |= VSC73XX_MAC_CFG_FDX;

	else

		/* In datasheet description ("Port Mode Procedure" in 5.6.2)

		 * this bit is configured only for half duplex.

		 */

		val |= VSC73XX_MAC_CFG_WEXC_DIS;



	/* This routine is described in the datasheet (below ARBDISC register

	 * description)
@@ -967,7 +972,6 @@ static void vsc73xx_mac_link_up(struct phylink_config *config, 
	get_random_bytes(&seed, 1);

	val |= seed << VSC73XX_MAC_CFG_SEED_OFFSET;

	val |= VSC73XX_MAC_CFG_SEED_LOAD;

	val |= VSC73XX_MAC_CFG_WEXC_DIS;



	/* Those bits are responsible for MTU only. Kernel takes care about MTU,

	 * let's enable +8 bytes frame length unconditionally.