Commit 6389e616 authored by Tomi Valkeinen's avatar Tomi Valkeinen Committed by Tomi Valkeinen
Browse files

drm/rcar-du: dsi: Fix PHY lock bit check 



The driver checks for bit 16 (using CLOCKSET1_LOCK define) in CLOCKSET1
register when waiting for the PPI clock. However, the right bit to check
is bit 17 (CLOCKSET1_LOCK_PHY define). Not only that, but there's
nothing in the documents for bit 16 for V3U nor V4H.

So, fix the check to use bit 17, and drop the define for bit 16.

Fixes: 15535831 ("drm: rcar-du: Add R-Car DSI driver")
Fixes: 11696c5e ("drm: Place Renesas drivers in a separate dir")
Cc: stable@vger.kernel.org
Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
Reviewed-by: default avatarLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241217-rcar-gh-dsi-v5-1-e77421093c05@ideasonboard.com
parent 4181576d

drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c

+1 −1
Original line number Diff line number Diff line
@@ -587,7 +587,7 @@ static int rcar_mipi_dsi_startup(struct rcar_mipi_dsi *dsi, 
	for (timeout = 10; timeout > 0; --timeout) {

		if ((rcar_mipi_dsi_read(dsi, PPICLSR) & PPICLSR_STPST) &&

		    (rcar_mipi_dsi_read(dsi, PPIDLSR) & PPIDLSR_STPST) &&

		    (rcar_mipi_dsi_read(dsi, CLOCKSET1) & CLOCKSET1_LOCK))

		    (rcar_mipi_dsi_read(dsi, CLOCKSET1) & CLOCKSET1_LOCK_PHY))

			break;



		usleep_range(1000, 2000);

drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h

+0 −1
Original line number Diff line number Diff line
@@ -142,7 +142,6 @@ 


#define CLOCKSET1			0x101c

#define CLOCKSET1_LOCK_PHY		(1 << 17)

#define CLOCKSET1_LOCK			(1 << 16)

#define CLOCKSET1_CLKSEL		(1 << 8)

#define CLOCKSET1_CLKINSEL_EXTAL	(0 << 2)

#define CLOCKSET1_CLKINSEL_DIG		(1 << 2)