Commit 651aabc9 authored by Yao Zi's avatar Yao Zi Committed by Heiko Stuebner
Browse files

clk: rockchip: Add PLL flag ROCKCHIP_PLL_FIXED_MODE 



RK3528 comes with a new PLL variant: its "PPLL", which mainly generates
clocks for the PCIe controller, operates in normal mode only. Let's
describe it with flag ROCKCHIP_PLL_FIXED_MODE and handle it in code.

Signed-off-by: default avatarYao Zi <ziyao@disroot.org>
Link: https://lore.kernel.org/r/20250217061142.38480-7-ziyao@disroot.org


Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 3688efdb

drivers/clk/rockchip/clk-pll.c

+6 −4
Original line number Diff line number Diff line
@@ -204,11 +204,13 @@ static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll, 
	rockchip_rk3036_pll_get_params(pll, &cur);

	cur.rate = 0;



	if (!(pll->flags & ROCKCHIP_PLL_FIXED_MODE)) {

		cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);

		if (cur_parent == PLL_MODE_NORM) {

			pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);

			rate_change_remuxed = 1;

		}

	}



	/* update pll values */

	writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK,

drivers/clk/rockchip/clk.h

+2 −0
Original line number Diff line number Diff line
@@ -444,6 +444,7 @@ struct rockchip_pll_rate_table { 
 * Flags:

 * ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the

 *	rate_table parameters and ajust them if necessary.

 * ROCKCHIP_PLL_FIXED_MODE - the pll operates in normal mode only

 */

struct rockchip_pll_clock {

	unsigned int		id;
@@ -461,6 +462,7 @@ struct rockchip_pll_clock { 
};



#define ROCKCHIP_PLL_SYNC_RATE		BIT(0)

#define ROCKCHIP_PLL_FIXED_MODE		BIT(1)



#define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift,	\

		_lshift, _pflags, _rtable)				\