Commit 652b08af authored by Cristian Birsan's avatar Cristian Birsan Committed by Nicolas Ferre
Browse files

ARM: at91: remove default values for PMC_PLL_ACR 



Remove default values for PMC PLL Analog Control Register(ACR) as the
values are specific for each SoC and PLL and load them from PLL
characteristics structure

Co-developed-by: default avatarAndrei Simion <andrei.simion@microchip.com>
Signed-off-by: default avatarAndrei Simion <andrei.simion@microchip.com>
Signed-off-by: default avatarCristian Birsan <cristian.birsan@microchip.com>
[nicolas.ferre@microchip.com: fix pll acr write sequence, preserve val]
Signed-off-by: default avatarNicolas Ferre <nicolas.ferre@microchip.com>
parent bfa2bddf

drivers/clk/at91/clk-sam9x60-pll.c

+2 −5
Original line number Diff line number Diff line
@@ -103,11 +103,8 @@ static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core) 
	    (cmul == frac->mul && cfrac == frac->frac))

		goto unlock;



	/* Recommended value for PMC_PLL_ACR */

	if (core->characteristics->upll)

		val = AT91_PMC_PLL_ACR_DEFAULT_UPLL;

	else

		val = AT91_PMC_PLL_ACR_DEFAULT_PLLA;

	/* Load recommended value for PMC_PLL_ACR */

	val = core->characteristics->acr;

	regmap_write(regmap, AT91_PMC_PLL_ACR, val);



	regmap_write(regmap, AT91_PMC_PLL_CTRL1,

include/linux/clk/at91_pmc.h

+0 −2
Original line number Diff line number Diff line
@@ -47,8 +47,6 @@ 
#define	AT91_PMC_PCSR		0x18			/* Peripheral Clock Status Register */



#define AT91_PMC_PLL_ACR	0x18			/* PLL Analog Control Register [for SAM9X60] */

#define		AT91_PMC_PLL_ACR_DEFAULT_UPLL	UL(0x12020010)	/* Default PLL ACR value for UPLL */

#define		AT91_PMC_PLL_ACR_DEFAULT_PLLA	UL(0x00020010)	/* Default PLL ACR value for PLLA */

#define		AT91_PMC_PLL_ACR_UTMIVR		(1 << 12)	/* UPLL Voltage regulator Control */

#define		AT91_PMC_PLL_ACR_UTMIBG		(1 << 13)	/* UPLL Bandgap Control */