Commit 654ac800 authored by Ajit Pandey's avatar Ajit Pandey Committed by Bjorn Andersson
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arm64: dts: qcom: sm4450: Add RPMh power domains support 



Add device node for RPMh power domains on Qualcomm SM4450 platform.

Signed-off-by: default avatarAjit Pandey <quic_ajipan@quicinc.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250417-sm4450_rpmhpd-v1-3-361846750d3a@quicinc.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 299038d8

arch/arm64/boot/dts/qcom/sm4450.dtsi

+68 −0
Original line number Diff line number Diff line
@@ -10,6 +10,8 @@ 
#include <dt-bindings/clock/qcom,sm4450-gpucc.h>

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/power/qcom,rpmhpd.h>

#include <dt-bindings/power/qcom-rpmpd.h>

#include <dt-bindings/soc/qcom,rpmh-rsc.h>



/ {
@@ -591,6 +593,72 @@ rpmhcc: clock-controller { 
				clocks = <&xo_board>;

				clock-names = "xo";

			};



			rpmhpd: power-controller {

				compatible = "qcom,sm4450-rpmhpd";

				#power-domain-cells = <1>;

				operating-points-v2 = <&rpmhpd_opp_table>;



				rpmhpd_opp_table: opp-table {

					compatible = "operating-points-v2";



					rpmhpd_opp_ret: opp-16 {

						opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;

					};



					rpmhpd_opp_min_svs: opp-48 {

						opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;

					};



					rpmhpd_opp_low_svs_d1: opp-56 {

						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;

					};



					rpmhpd_opp_low_svs: opp-64 {

						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;

					};



					rpmhpd_opp_low_svs_l1: opp-80 {

						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;

					};



					rpmhpd_opp_low_svs_l2: opp-96 {

						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L2>;

					};



					rpmhpd_opp_svs: opp-128 {

						opp-level = <RPMH_REGULATOR_LEVEL_SVS>;

					};



					rpmhpd_opp_svs_l1: opp-192 {

						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;

					};



					rpmhpd_opp_svs_l2: opp-224 {

						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;

					};



					rpmhpd_opp_nom: opp-256 {

						opp-level = <RPMH_REGULATOR_LEVEL_NOM>;

					};



					rpmhpd_opp_nom_l1: opp-320 {

						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;

					};



					rpmhpd_opp_nom_l2: opp-336 {

						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;

					};



					rpmhpd_opp_turbo: opp-384 {

						opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;

					};



					rpmhpd_opp_turbo_l1: opp-416 {

						opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;

					};

				};

			};

		};



		cpufreq_hw: cpufreq@17d91000 {