Commit 656ef2ea authored by Atish Patra's avatar Atish Patra Committed by Anup Patel
Browse files

drivers/perf: riscv: Add raw event v2 support 



SBI v3.0 introduced a new raw event type that allows wider
mhpmeventX width to be programmed via CFG_MATCH.

Use the raw event v2 if SBI v3.0 is available.

Reviewed-by: default avatarAnup Patel <anup@brainfault.org>
Signed-off-by: default avatarAtish Patra <atishp@rivosinc.com>
Acked-by: default avatarPaul Walmsley <pjw@kernel.org>
Link: https://lore.kernel.org/r/20250909-pmu_event_info-v6-2-d8f80cacb884@rivosinc.com


Signed-off-by: default avatarAnup Patel <anup@brainfault.org>
parent 8c8d0f00

arch/riscv/include/asm/sbi.h

+4 −0
Original line number Diff line number Diff line
@@ -161,7 +161,10 @@ struct riscv_pmu_snapshot_data { 


#define RISCV_PMU_RAW_EVENT_MASK GENMASK_ULL(47, 0)

#define RISCV_PMU_PLAT_FW_EVENT_MASK GENMASK_ULL(61, 0)

/* SBI v3.0 allows extended hpmeventX width value */

#define RISCV_PMU_RAW_EVENT_V2_MASK GENMASK_ULL(55, 0)

#define RISCV_PMU_RAW_EVENT_IDX 0x20000

#define RISCV_PMU_RAW_EVENT_V2_IDX 0x30000

#define RISCV_PLAT_FW_EVENT	0xFFFF



/** General pmu event codes specified in SBI PMU extension */
@@ -219,6 +222,7 @@ enum sbi_pmu_event_type { 
	SBI_PMU_EVENT_TYPE_HW = 0x0,

	SBI_PMU_EVENT_TYPE_CACHE = 0x1,

	SBI_PMU_EVENT_TYPE_RAW = 0x2,

	SBI_PMU_EVENT_TYPE_RAW_V2 = 0x3,

	SBI_PMU_EVENT_TYPE_FW = 0xf,

};

drivers/perf/riscv_pmu_sbi.c

+11 −5
Original line number Diff line number Diff line
@@ -59,7 +59,7 @@ asm volatile(ALTERNATIVE( \ 
#define PERF_EVENT_FLAG_USER_ACCESS	BIT(SYSCTL_USER_ACCESS)

#define PERF_EVENT_FLAG_LEGACY		BIT(SYSCTL_LEGACY)



PMU_FORMAT_ATTR(event, "config:0-47");

PMU_FORMAT_ATTR(event, "config:0-55");

PMU_FORMAT_ATTR(firmware, "config:62-63");



static bool sbi_v2_available;
@@ -527,8 +527,10 @@ static int pmu_sbi_event_map(struct perf_event *event, u64 *econfig) 
		break;

	case PERF_TYPE_RAW:

		/*

		 * As per SBI specification, the upper 16 bits must be unused

		 * for a hardware raw event.

		 * As per SBI v0.3 specification,

		 *  -- the upper 16 bits must be unused for a hardware raw event.

		 * As per SBI v2.0 specification,

		 *  -- the upper 8 bits must be unused for a hardware raw event.

		 * Bits 63:62 are used to distinguish between raw events

		 * 00 - Hardware raw event

		 * 10 - SBI firmware events
@@ -537,8 +539,12 @@ static int pmu_sbi_event_map(struct perf_event *event, u64 *econfig) 


		switch (config >> 62) {

		case 0:

			/* Return error any bits [48-63] is set  as it is not allowed by the spec */

			if (!(config & ~RISCV_PMU_RAW_EVENT_MASK)) {

			if (sbi_v3_available) {

				if (!(config & ~RISCV_PMU_RAW_EVENT_V2_MASK)) {

					*econfig = config & RISCV_PMU_RAW_EVENT_V2_MASK;

					ret = RISCV_PMU_RAW_EVENT_V2_IDX;

				}

			} else if (!(config & ~RISCV_PMU_RAW_EVENT_MASK)) {

				*econfig = config & RISCV_PMU_RAW_EVENT_MASK;

				ret = RISCV_PMU_RAW_EVENT_IDX;

			}