Commit 65c02404 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915/gvt: Clean up zero initializers



Just use a simple {} to zero initialize arrays/structs instead
of the hodgepodge of stuff we are using currently.

Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Zhi Wang <zhi.a.wang@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231012122442.15718-7-ville.syrjala@linux.intel.com


Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
parent c610e841
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+1 −1
Original line number Diff line number Diff line
@@ -3047,7 +3047,7 @@ static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx)

static int combine_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
{
	u32 per_ctx_start[CACHELINE_DWORDS] = {0};
	u32 per_ctx_start[CACHELINE_DWORDS] = {};
	unsigned char *bb_start_sva;

	if (!wa_ctx->per_ctx.valid)
+3 −3
Original line number Diff line number Diff line
@@ -56,7 +56,7 @@ static const struct pixel_format bdw_pixel_formats[] = {
	{DRM_FORMAT_XBGR8888, 32, "32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"},

	/* non-supported format has bpp default to 0 */
	{0, 0, NULL},
	{}
};

static const struct pixel_format skl_pixel_formats[] = {
@@ -76,7 +76,7 @@ static const struct pixel_format skl_pixel_formats[] = {
	{DRM_FORMAT_XRGB2101010, 32, "32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"},

	/* non-supported format has bpp default to 0 */
	{0, 0, NULL},
	{}
};

static int bdw_format_to_drm(int format)
@@ -293,7 +293,7 @@ static const struct cursor_mode_format cursor_pixel_formats[] = {
	{DRM_FORMAT_ARGB8888, 32, 64, 64, "64x64 32bpp ARGB"},

	/* non-supported format has bpp default to 0 */
	{0, 0, 0, 0, NULL},
	{}
};

static int cursor_mode_to_drm(int mode)
+1 −1
Original line number Diff line number Diff line
@@ -538,7 +538,7 @@ static u32 bxt_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port)
	int refclk = vgpu->gvt->gt->i915->display.dpll.ref_clks.nssc;
	enum dpio_phy phy = DPIO_PHY0;
	enum dpio_channel ch = DPIO_CH0;
	struct dpll clock = {0};
	struct dpll clock = {};
	u32 temp;

	/* Port to PHY mapping is fixed, see bxt_ddi_phy_info{} */