Merge tag 'v4.20-rc6' into i2c/for-5.0 (66693960) · Commits · git / linux-nf

Documentation/ABI/testing/sysfs-class-net-dsa

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		What: /sys/class/net/<iface>/tagging
		What: /sys/class/net/<iface>/dsa/tagging
		Date: August 2018
		KernelVersion: 4.20
		Contact: netdev@vger.kernel.org

Documentation/admin-guide/kernel-parameters.txt

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		@@ -856,7 +856,8 @@
		causing system reset or hang due to sending
		INIT from AP to BSP.

		disable_counter_freezing [HW]
		perf_v4_pmi= [X86,INTEL]
		Format: <bool>
		Disable Intel PMU counter freezing feature.
		The feature only exists starting from
		Arch Perfmon v4 (Skylake and newer).
		@@ -3504,6 +3505,10 @@
		before loading.
		See Documentation/blockdev/ramdisk.txt.

		psi= [KNL] Enable or disable pressure stall information
		tracking.
		Format: <bool>

		psmouse.proto= [HW,MOUSE] Highest PS2 mouse protocol extension to
		probe for; one of (bare\|imps\|exps\|lifebook\|any).
		psmouse.rate= [HW,MOUSE] Set desired mouse report rate, in reports
		@@ -4194,9 +4199,13 @@

		spectre_v2= [X86] Control mitigation of Spectre variant 2
		(indirect branch speculation) vulnerability.
		The default operation protects the kernel from
		user space attacks.

		on - unconditionally enable
		off - unconditionally disable
		on - unconditionally enable, implies
		spectre_v2_user=on
		off - unconditionally disable, implies
		spectre_v2_user=off
		auto - kernel detects whether your CPU model is
		vulnerable

		@@ -4206,6 +4215,12 @@
		CONFIG_RETPOLINE configuration option, and the
		compiler with which the kernel was built.

		Selecting 'on' will also enable the mitigation
		against user space to user space task attacks.

		Selecting 'off' will disable both the kernel and
		the user space protections.

		Specific mitigations can also be selected manually:

		retpoline - replace indirect branches
		@@ -4215,6 +4230,48 @@
		Not specifying this option is equivalent to
		spectre_v2=auto.

		spectre_v2_user=
		[X86] Control mitigation of Spectre variant 2
		(indirect branch speculation) vulnerability between
		user space tasks

		on - Unconditionally enable mitigations. Is
		enforced by spectre_v2=on

		off - Unconditionally disable mitigations. Is
		enforced by spectre_v2=off

		prctl - Indirect branch speculation is enabled,
		but mitigation can be enabled via prctl
		per thread. The mitigation control state
		is inherited on fork.

		prctl,ibpb
		- Like "prctl" above, but only STIBP is
		controlled per thread. IBPB is issued
		always when switching between different user
		space processes.

		seccomp
		- Same as "prctl" above, but all seccomp
		threads will enable the mitigation unless
		they explicitly opt out.

		seccomp,ibpb
		- Like "seccomp" above, but only STIBP is
		controlled per thread. IBPB is issued
		always when switching between different
		user space processes.

		auto - Kernel selects the mitigation depending on
		the available CPU features and vulnerability.

		Default mitigation:
		If CONFIG_SECCOMP=y then "seccomp", otherwise "prctl"

		Not specifying this option is equivalent to
		spectre_v2_user=auto.

		spec_store_bypass_disable=
		[HW] Control Speculative Store Bypass (SSB) Disable mitigation
		(Speculative Store Bypass vulnerability)

Documentation/arm64/silicon-errata.txt

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		@@ -57,6 +57,7 @@ stable kernels.
		\| ARM \| Cortex-A73 \| #858921 \| ARM64_ERRATUM_858921 \|
		\| ARM \| Cortex-A55 \| #1024718 \| ARM64_ERRATUM_1024718 \|
		\| ARM \| Cortex-A76 \| #1188873 \| ARM64_ERRATUM_1188873 \|
		\| ARM \| Cortex-A76 \| #1286807 \| ARM64_ERRATUM_1286807 \|
		\| ARM \| MMU-500 \| #841119,#826419 \| N/A \|
		\| \| \| \| \|
		\| Cavium \| ThunderX ITS \| #22375, #24313 \| CAVIUM_ERRATUM_22375 \|

Documentation/devicetree/bindings/clock/clock-bindings.txt

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		@@ -168,3 +168,19 @@ a shared clock is forbidden.

		Configuration of common clocks, which affect multiple consumer devices can
		be similarly specified in the clock provider node.

		==Protected clocks==

		Some platforms or firmwares may not fully expose all the clocks to the OS, such
		as in situations where those clks are used by drivers running in ARM secure
		execution levels. Such a configuration can be specified in device tree with the
		protected-clocks property in the form of a clock specifier list. This property should
		only be specified in the node that is providing the clocks being protected:

		clock-controller@a000f000 {
		compatible = "vendor,clk95;
		reg = <0xa000f000 0x1000>
		#clocks-cells = <1>;
		...
		protected-clocks = <UART3_CLK>, <SPI5_CLK>;
		};

Documentation/devicetree/bindings/input/input-reset.txt

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		@@ -12,7 +12,7 @@ The /chosen node should contain a 'linux,sysrq-reset-seq' child node to define
		a set of keys.

		Required property:
		sysrq-reset-seq: array of Linux keycodes, one keycode per cell.
		keyset: array of Linux keycodes, one keycode per cell.

		Optional property:
		timeout-ms: duration keys must be pressed together in milliseconds before

Original line number	Diff line number	Diff line
		@@ -57,6 +57,7 @@ stable kernels.
		\| ARM \| Cortex-A73 \| #858921 \| ARM64_ERRATUM_858921 \|
		\| ARM \| Cortex-A55 \| #1024718 \| ARM64_ERRATUM_1024718 \|
		\| ARM \| Cortex-A76 \| #1188873 \| ARM64_ERRATUM_1188873 \|
		\| ARM \| Cortex-A76 \| #1286807 \| ARM64_ERRATUM_1286807 \|
		\| ARM \| MMU-500 \| #841119,#826419 \| N/A \|
		\| \| \| \| \|
		\| Cavium \| ThunderX ITS \| #22375, #24313 \| CAVIUM_ERRATUM_22375 \|