Commit 674b0ddb authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi 

Pull SCSI updates from James Bottomley:
 "Usual driver updates (ufs, mpi3mr, lpfc, pm80xx, mpt3sas) plus
  assorted cleanups and fixes.

  The only core update is to sd.c and is mostly cosmetic"

* tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi: (105 commits)
  scsi: MAINTAINERS: Update FC element owners
  scsi: mpt3sas: Update driver version to 54.100.00.00
  scsi: mpt3sas: Add support for 22.5 Gbps SAS link rate
  scsi: mpt3sas: Suppress unnecessary IOCLogInfo on CONFIG_INVALID_PAGE
  scsi: mpt3sas: Fix crash in transport port remove by using ioc_info()
  scsi: ufs: ufs-qcom: Add support for limiting HS gear and rate
  scsi: ufs: pltfrm: Add DT support to limit HS gear and gear rate
  scsi: ufs: ufs-qcom: Remove redundant re-assignment to hs_rate
  scsi: ufs: dt-bindings: Document gear and rate limit properties
  scsi: ufs: core: Fix data race in CPU latency PM QoS request handling
  scsi: libfc: Fix potential buffer overflow in fc_ct_ms_fill()
  scsi: storvsc: Remove redundant ternary operators
  scsi: ufs: core: Change MCQ interrupt enable flow
  scsi: smartpqi: Replace kmalloc() + copy_from_user() with memdup_user()
  scsi: hpsa: Replace kmalloc() + copy_from_user() with memdup_user()
  scsi: hpsa: Fix potential memory leak in hpsa_big_passthru_ioctl()
  scsi: lpfc: Copyright updates for 14.4.0.11 patches
  scsi: lpfc: Update lpfc version to 14.4.0.11
  scsi: lpfc: Convert debugfs directory counts from atomic to unsigned int
  scsi: lpfc: Clean up extraneous phba dentries
  ...
parents 7dbec0bb fb641516

Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/ufs/qcom,sc7180-ufshc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm SC7180 and Other SoCs UFS Controllers



maintainers:

  - Bjorn Andersson <bjorn.andersson@linaro.org>



# Select only our matches, not all jedec,ufs-2.0

select:

  properties:

    compatible:

      contains:

        enum:

          - qcom,msm8998-ufshc

          - qcom,qcs8300-ufshc

          - qcom,sa8775p-ufshc

          - qcom,sc7180-ufshc

          - qcom,sc7280-ufshc

          - qcom,sc8180x-ufshc

          - qcom,sc8280xp-ufshc

          - qcom,sm8250-ufshc

          - qcom,sm8350-ufshc

          - qcom,sm8450-ufshc

          - qcom,sm8550-ufshc

  required:

    - compatible



properties:

  compatible:

    items:

      - enum:

          - qcom,msm8998-ufshc

          - qcom,qcs8300-ufshc

          - qcom,sa8775p-ufshc

          - qcom,sc7180-ufshc

          - qcom,sc7280-ufshc

          - qcom,sc8180x-ufshc

          - qcom,sc8280xp-ufshc

          - qcom,sm8250-ufshc

          - qcom,sm8350-ufshc

          - qcom,sm8450-ufshc

          - qcom,sm8550-ufshc

      - const: qcom,ufshc

      - const: jedec,ufs-2.0



  reg:

    maxItems: 1



  reg-names:

    items:

      - const: std



  clocks:

    minItems: 7

    maxItems: 8



  clock-names:

    minItems: 7

    items:

      - const: core_clk

      - const: bus_aggr_clk

      - const: iface_clk

      - const: core_clk_unipro

      - const: ref_clk

      - const: tx_lane0_sync_clk

      - const: rx_lane0_sync_clk

      - const: rx_lane1_sync_clk



  qcom,ice:

    $ref: /schemas/types.yaml#/definitions/phandle

    description: phandle to the Inline Crypto Engine node



required:

  - compatible

  - reg



allOf:

  - $ref: qcom,ufs-common.yaml



  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,sc7180-ufshc

    then:

      properties:

        clocks:

          maxItems: 7

        clock-names:

          maxItems: 7

    else:

      properties:

        clocks:

          minItems: 8

        clock-names:

          minItems: 8



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,gcc-sm8450.h>

    #include <dt-bindings/clock/qcom,rpmh.h>

    #include <dt-bindings/gpio/gpio.h>

    #include <dt-bindings/interconnect/qcom,sm8450.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    soc {

        #address-cells = <2>;

        #size-cells = <2>;



        ufs@1d84000 {

            compatible = "qcom,sm8450-ufshc", "qcom,ufshc",

                         "jedec,ufs-2.0";

            reg = <0x0 0x01d84000 0x0 0x3000>;

            interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;

            phys = <&ufs_mem_phy_lanes>;

            phy-names = "ufsphy";

            lanes-per-direction = <2>;

            #reset-cells = <1>;

            resets = <&gcc GCC_UFS_PHY_BCR>;

            reset-names = "rst";

            reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;



            vcc-supply = <&vreg_l7b_2p5>;

            vcc-max-microamp = <1100000>;

            vccq-supply = <&vreg_l9b_1p2>;

            vccq-max-microamp = <1200000>;



            power-domains = <&gcc UFS_PHY_GDSC>;

            iommus = <&apps_smmu 0xe0 0x0>;

            interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,

                            <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;

            interconnect-names = "ufs-ddr", "cpu-ufs";



            clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,

                     <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,

                     <&gcc GCC_UFS_PHY_AHB_CLK>,

                     <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,

                     <&rpmhcc RPMH_CXO_CLK>,

                     <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,

                     <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,

                     <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;

            clock-names = "core_clk",

                          "bus_aggr_clk",

                          "iface_clk",

                          "core_clk_unipro",

                          "ref_clk",

                          "tx_lane0_sync_clk",

                          "rx_lane0_sync_clk",

                          "rx_lane1_sync_clk";

            freq-table-hz = <75000000 300000000>,

                            <0 0>,

                            <0 0>,

                            <75000000 300000000>,

                            <75000000 300000000>,

                            <0 0>,

                            <0 0>,

                            <0 0>;

            qcom,ice = <&ice>;

        };

    };

Documentation/devicetree/bindings/ufs/qcom,sm8650-ufshc.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/ufs/qcom,sm8650-ufshc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm SM8650 and Other SoCs UFS Controllers



maintainers:

  - Bjorn Andersson <bjorn.andersson@linaro.org>



# Select only our matches, not all jedec,ufs-2.0

select:

  properties:

    compatible:

      contains:

        enum:

          - qcom,sm8650-ufshc

          - qcom,sm8750-ufshc

  required:

    - compatible



properties:

  compatible:

    items:

      - enum:

          - qcom,sm8650-ufshc

          - qcom,sm8750-ufshc

      - const: qcom,ufshc

      - const: jedec,ufs-2.0



  reg:

    minItems: 1

    maxItems: 2



  reg-names:

    minItems: 1

    items:

      - const: std

      - const: mcq



  clocks:

    minItems: 8

    maxItems: 8



  clock-names:

    items:

      - const: core_clk

      - const: bus_aggr_clk

      - const: iface_clk

      - const: core_clk_unipro

      - const: ref_clk

      - const: tx_lane0_sync_clk

      - const: rx_lane0_sync_clk

      - const: rx_lane1_sync_clk



  qcom,ice:

    $ref: /schemas/types.yaml#/definitions/phandle

    description: phandle to the Inline Crypto Engine node



required:

  - compatible

  - reg



allOf:

  - $ref: qcom,ufs-common.yaml



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,sm8650-gcc.h>

    #include <dt-bindings/clock/qcom,sm8650-tcsr.h>

    #include <dt-bindings/clock/qcom,rpmh.h>

    #include <dt-bindings/gpio/gpio.h>

    #include <dt-bindings/interconnect/qcom,icc.h>

    #include <dt-bindings/interconnect/qcom,sm8650-rpmh.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    soc {

        #address-cells = <2>;

        #size-cells = <2>;



        ufshc@1d84000 {

            compatible = "qcom,sm8650-ufshc", "qcom,ufshc", "jedec,ufs-2.0";

            reg = <0x0 0x01d84000 0x0 0x3000>;



            interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;



            clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,

                     <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,

                     <&gcc GCC_UFS_PHY_AHB_CLK>,

                     <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,

                     <&tcsr TCSR_UFS_PAD_CLKREF_EN>,

                     <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,

                     <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,

                     <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;

            clock-names = "core_clk",

                          "bus_aggr_clk",

                          "iface_clk",

                          "core_clk_unipro",

                          "ref_clk",

                          "tx_lane0_sync_clk",

                          "rx_lane0_sync_clk",

                          "rx_lane1_sync_clk";



            resets = <&gcc GCC_UFS_PHY_BCR>;

            reset-names = "rst";

            reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;



            interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS

                             &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,

                            <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY

                             &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;

            interconnect-names = "ufs-ddr",

                         "cpu-ufs";



            power-domains = <&gcc UFS_PHY_GDSC>;

            required-opps = <&rpmhpd_opp_nom>;



            operating-points-v2 = <&ufs_opp_table>;



            iommus = <&apps_smmu 0x60 0>;



            lanes-per-direction = <2>;

            qcom,ice = <&ice>;



            phys = <&ufs_mem_phy>;

            phy-names = "ufsphy";



            #reset-cells = <1>;



            vcc-supply = <&vreg_l7b_2p5>;

            vcc-max-microamp = <1100000>;

            vccq-supply = <&vreg_l9b_1p2>;

            vccq-max-microamp = <1200000>;



            ufs_opp_table: opp-table {

                compatible = "operating-points-v2";



                opp-100000000 {

                    opp-hz = /bits/ 64 <100000000>,

                             /bits/ 64 <0>,

                             /bits/ 64 <0>,

                             /bits/ 64 <100000000>,

                             /bits/ 64 <0>,

                             /bits/ 64 <0>,

                             /bits/ 64 <0>,

                             /bits/ 64 <0>;

                    required-opps = <&rpmhpd_opp_low_svs>;

                };



                opp-201500000 {

                    opp-hz = /bits/ 64 <201500000>,

                             /bits/ 64 <0>,

                             /bits/ 64 <0>,

                             /bits/ 64 <201500000>,

                             /bits/ 64 <0>,

                             /bits/ 64 <0>,

                             /bits/ 64 <0>,

                             /bits/ 64 <0>;

                    required-opps = <&rpmhpd_opp_svs>;

                };



                opp-403000000 {

                    opp-hz = /bits/ 64 <403000000>,

                             /bits/ 64 <0>,

                             /bits/ 64 <0>,

                             /bits/ 64 <403000000>,

                             /bits/ 64 <0>,

                             /bits/ 64 <0>,

                             /bits/ 64 <0>,

                             /bits/ 64 <0>;

                    required-opps = <&rpmhpd_opp_nom>;

                };

            };

        };

    };

Documentation/devicetree/bindings/ufs/qcom,ufs-common.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/ufs/qcom,ufs-common.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Universal Flash Storage (UFS) Controller Common Properties



maintainers:

  - Bjorn Andersson <bjorn.andersson@linaro.org>



properties:

  clocks:

    minItems: 7

    maxItems: 9



  clock-names:

    minItems: 7

    maxItems: 9



  dma-coherent: true



  interconnects:

    minItems: 2

    maxItems: 2



  interconnect-names:

    items:

      - const: ufs-ddr

      - const: cpu-ufs



  iommus:

    minItems: 1

    maxItems: 2



  phys:

    maxItems: 1



  phy-names:

    items:

      - const: ufsphy



  power-domains:

    maxItems: 1



  required-opps:

    maxItems: 1



  resets:

    maxItems: 1



  '#reset-cells':

    const: 1



  reset-names:

    items:

      - const: rst



  reset-gpios:

    maxItems: 1

    description:

      GPIO connected to the RESET pin of the UFS memory device.



allOf:

  - $ref: ufs-common.yaml



additionalProperties: true

Documentation/devicetree/bindings/ufs/qcom,ufs.yaml

+34 −151
Original line number Diff line number Diff line
@@ -15,7 +15,15 @@ select: 
  properties:

    compatible:

      contains:

        const: qcom,ufshc

        enum:

          - qcom,msm8994-ufshc

          - qcom,msm8996-ufshc

          - qcom,qcs615-ufshc

          - qcom,sdm845-ufshc

          - qcom,sm6115-ufshc

          - qcom,sm6125-ufshc

          - qcom,sm6350-ufshc

          - qcom,sm8150-ufshc

  required:

    - compatible
@@ -25,61 +33,15 @@ properties: 
      - enum:

          - qcom,msm8994-ufshc

          - qcom,msm8996-ufshc

          - qcom,msm8998-ufshc

          - qcom,qcs615-ufshc

          - qcom,qcs8300-ufshc

          - qcom,sa8775p-ufshc

          - qcom,sc7180-ufshc

          - qcom,sc7280-ufshc

          - qcom,sc8180x-ufshc

          - qcom,sc8280xp-ufshc

          - qcom,sdm845-ufshc

          - qcom,sm6115-ufshc

          - qcom,sm6125-ufshc

          - qcom,sm6350-ufshc

          - qcom,sm8150-ufshc

          - qcom,sm8250-ufshc

          - qcom,sm8350-ufshc

          - qcom,sm8450-ufshc

          - qcom,sm8550-ufshc

          - qcom,sm8650-ufshc

          - qcom,sm8750-ufshc

      - const: qcom,ufshc

      - const: jedec,ufs-2.0



  clocks:

    minItems: 7

    maxItems: 9



  clock-names:

    minItems: 7

    maxItems: 9



  dma-coherent: true



  interconnects:

    minItems: 2

    maxItems: 2



  interconnect-names:

    items:

      - const: ufs-ddr

      - const: cpu-ufs



  iommus:

    minItems: 1

    maxItems: 2



  phys:

    maxItems: 1



  phy-names:

    items:

      - const: ufsphy



  power-domains:

    maxItems: 1



  qcom,ice:

    $ref: /schemas/types.yaml#/definitions/phandle

    description: phandle to the Inline Crypto Engine node
@@ -93,93 +55,12 @@ properties: 
      - const: std

      - const: ice



  required-opps:

    maxItems: 1



  resets:

    maxItems: 1



  '#reset-cells':

    const: 1



  reset-names:

    items:

      - const: rst



  reset-gpios:

    maxItems: 1

    description:

      GPIO connected to the RESET pin of the UFS memory device.



required:

  - compatible

  - reg



allOf:

  - $ref: ufs-common.yaml



  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,sc7180-ufshc

    then:

      properties:

        clocks:

          minItems: 7

          maxItems: 7

        clock-names:

          items:

            - const: core_clk

            - const: bus_aggr_clk

            - const: iface_clk

            - const: core_clk_unipro

            - const: ref_clk

            - const: tx_lane0_sync_clk

            - const: rx_lane0_sync_clk

        reg:

          maxItems: 1

        reg-names:

          maxItems: 1



  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,msm8998-ufshc

              - qcom,qcs8300-ufshc

              - qcom,sa8775p-ufshc

              - qcom,sc7280-ufshc

              - qcom,sc8180x-ufshc

              - qcom,sc8280xp-ufshc

              - qcom,sm8250-ufshc

              - qcom,sm8350-ufshc

              - qcom,sm8450-ufshc

              - qcom,sm8550-ufshc

              - qcom,sm8650-ufshc

              - qcom,sm8750-ufshc

    then:

      properties:

        clocks:

          minItems: 8

          maxItems: 8

        clock-names:

          items:

            - const: core_clk

            - const: bus_aggr_clk

            - const: iface_clk

            - const: core_clk_unipro

            - const: ref_clk

            - const: tx_lane0_sync_clk

            - const: rx_lane0_sync_clk

            - const: rx_lane1_sync_clk

        reg:

          minItems: 1

          maxItems: 1

        reg-names:

          maxItems: 1

  - $ref: qcom,ufs-common.yaml



  - if:

      properties:
@@ -297,10 +178,10 @@ unevaluatedProperties: false 


examples:

  - |

    #include <dt-bindings/clock/qcom,gcc-sm8450.h>

    #include <dt-bindings/clock/qcom,gcc-sm8150.h>

    #include <dt-bindings/clock/qcom,rpmh.h>

    #include <dt-bindings/gpio/gpio.h>

    #include <dt-bindings/interconnect/qcom,sm8450.h>

    #include <dt-bindings/interconnect/qcom,sm8150.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    soc {
@@ -308,9 +189,12 @@ examples: 
        #size-cells = <2>;



        ufs@1d84000 {

            compatible = "qcom,sm8450-ufshc", "qcom,ufshc",

            compatible = "qcom,sm8150-ufshc", "qcom,ufshc",

                         "jedec,ufs-2.0";

            reg = <0 0x01d84000 0 0x3000>;

            reg = <0x0 0x01d84000 0x0 0x2500>,

                  <0x0 0x01d90000 0x0 0x8000>;

            reg-names = "std", "ice";



            interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;

            phys = <&ufs_mem_phy_lanes>;

            phy-names = "ufsphy";
@@ -326,19 +210,8 @@ examples: 
            vccq-max-microamp = <1200000>;



            power-domains = <&gcc UFS_PHY_GDSC>;

            iommus = <&apps_smmu 0xe0 0x0>;

            interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,

                            <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;

            interconnect-names = "ufs-ddr", "cpu-ufs";

            iommus = <&apps_smmu 0x300 0>;



            clock-names = "core_clk",

                          "bus_aggr_clk",

                          "iface_clk",

                          "core_clk_unipro",

                          "ref_clk",

                          "tx_lane0_sync_clk",

                          "rx_lane0_sync_clk",

                          "rx_lane1_sync_clk";

            clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,

                     <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,

                     <&gcc GCC_UFS_PHY_AHB_CLK>,
@@ -346,15 +219,25 @@ examples: 
                     <&rpmhcc RPMH_CXO_CLK>,

                     <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,

                     <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,

                     <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;

            freq-table-hz = <75000000 300000000>,

                     <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,

                     <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;

            clock-names = "core_clk",

                          "bus_aggr_clk",

                          "iface_clk",

                          "core_clk_unipro",

                          "ref_clk",

                          "tx_lane0_sync_clk",

                          "rx_lane0_sync_clk",

                          "rx_lane1_sync_clk",

                          "ice_core_clk";

            freq-table-hz = <37500000 300000000>,

                            <0 0>,

                            <0 0>,

                            <37500000 300000000>,

                            <0 0>,

                            <0 0>,

                            <75000000 300000000>,

                            <75000000 300000000>,

                            <0 0>,

                            <0 0>,

                            <0 0>;

            qcom,ice = <&ice>;

                            <0 300000000>;

        };

    };

Documentation/devicetree/bindings/ufs/ufs-common.yaml

+16 −0
Original line number Diff line number Diff line
@@ -89,6 +89,22 @@ properties: 


  msi-parent: true



  limit-hs-gear:

    $ref: /schemas/types.yaml#/definitions/uint32

    minimum: 1

    maximum: 6

    default: 6

    description:

      Restricts the maximum HS gear used in both TX and RX directions.



  limit-gear-rate:

    $ref: /schemas/types.yaml#/definitions/string

    enum: [rate-a, rate-b]

    default: rate-b

    description:

      Restricts the UFS controller to rate-a or rate-b for both TX and

      RX directions.



dependencies:

  freq-table-hz: [ clocks ]

  operating-points-v2: [ clocks, clock-names ]