Commit 6912ec91 authored by Nicolin Chen's avatar Nicolin Chen Committed by Will Deacon
Browse files

iommu/arm-smmu-v3: Support IOMMU_GET_HW_INFO via struct arm_smmu_hw_info 



For virtualization cases the IDR/IIDR/AIDR values of the actual SMMU
instance need to be available to the VMM so it can construct an
appropriate vSMMUv3 that reflects the correct HW capabilities.

For userspace page tables these values are required to constrain the valid
values within the CD table and the IOPTEs.

The kernel does not sanitize these values. If building a VMM then
userspace is required to only forward bits into a VM that it knows it can
implement. Some bits will also require a VMM to detect if appropriate
kernel support is available such as for ATS and BTM.

Start a new file and kconfig for the advanced iommufd support. This lets
it be compiled out for kernels that are not intended to support
virtualization, and allows distros to leave it disabled until they are
shipping a matching qemu too.

Tested-by: default avatarNicolin Chen <nicolinc@nvidia.com>
Signed-off-by: default avatarNicolin Chen <nicolinc@nvidia.com>
Reviewed-by: default avatarKevin Tian <kevin.tian@intel.com>
Reviewed-by: default avatarJerry Snitselaar <jsnitsel@redhat.com>
Reviewed-by: default avatarDonald Dutile <ddutile@redhat.com>
Signed-off-by: default avatarJason Gunthorpe <jgg@nvidia.com>
Link: https://lore.kernel.org/r/5-v4-9e99b76f3518+3a8-smmuv3_nesting_jgg@nvidia.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent e89573cf

drivers/iommu/Kconfig

+9 −0
Original line number Diff line number Diff line
@@ -415,6 +415,15 @@ config ARM_SMMU_V3_SVA 
	  Say Y here if your system supports SVA extensions such as PCIe PASID

	  and PRI.



config ARM_SMMU_V3_IOMMUFD

	bool "Enable IOMMUFD features for ARM SMMUv3 (EXPERIMENTAL)"

	depends on IOMMUFD

	help

	  Support for IOMMUFD features intended to support virtual machines

	  with accelerated virtual IOMMUs.



	  Say Y here if you are doing development and testing on this feature.



config ARM_SMMU_V3_KUNIT_TEST

	tristate "KUnit tests for arm-smmu-v3 driver"  if !KUNIT_ALL_TESTS

	depends on KUNIT

drivers/iommu/arm/arm-smmu-v3/Makefile

+1 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

obj-$(CONFIG_ARM_SMMU_V3) += arm_smmu_v3.o

arm_smmu_v3-y := arm-smmu-v3.o

arm_smmu_v3-$(CONFIG_ARM_SMMU_V3_IOMMUFD) += arm-smmu-v3-iommufd.o

arm_smmu_v3-$(CONFIG_ARM_SMMU_V3_SVA) += arm-smmu-v3-sva.o

arm_smmu_v3-$(CONFIG_TEGRA241_CMDQV) += tegra241-cmdqv.o

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c

0 → 100644
+31 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES

 */



#include <uapi/linux/iommufd.h>



#include "arm-smmu-v3.h"



void *arm_smmu_hw_info(struct device *dev, u32 *length, u32 *type)

{

	struct arm_smmu_master *master = dev_iommu_priv_get(dev);

	struct iommu_hw_info_arm_smmuv3 *info;

	u32 __iomem *base_idr;

	unsigned int i;



	info = kzalloc(sizeof(*info), GFP_KERNEL);

	if (!info)

		return ERR_PTR(-ENOMEM);



	base_idr = master->smmu->base + ARM_SMMU_IDR0;

	for (i = 0; i <= 5; i++)

		info->idr[i] = readl_relaxed(base_idr + i);

	info->iidr = readl_relaxed(master->smmu->base + ARM_SMMU_IIDR);

	info->aidr = readl_relaxed(master->smmu->base + ARM_SMMU_AIDR);



	*length = sizeof(*info);

	*type = IOMMU_HW_INFO_TYPE_ARM_SMMUV3;



	return info;

}

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c

+1 −0
Original line number Diff line number Diff line
@@ -3506,6 +3506,7 @@ static struct iommu_ops arm_smmu_ops = { 
	.identity_domain	= &arm_smmu_identity_domain,

	.blocked_domain		= &arm_smmu_blocked_domain,

	.capable		= arm_smmu_capable,

	.hw_info		= arm_smmu_hw_info,

	.domain_alloc_paging    = arm_smmu_domain_alloc_paging,

	.domain_alloc_sva       = arm_smmu_sva_domain_alloc,

	.domain_alloc_user	= arm_smmu_domain_alloc_user,

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

+9 −0
Original line number Diff line number Diff line
@@ -81,6 +81,8 @@ struct arm_smmu_device; 
#define IIDR_REVISION			GENMASK(15, 12)

#define IIDR_IMPLEMENTER		GENMASK(11, 0)



#define ARM_SMMU_AIDR			0x1C



#define ARM_SMMU_CR0			0x20

#define CR0_ATSCHK			(1 << 4)

#define CR0_CMDQEN			(1 << 3)
@@ -956,4 +958,11 @@ tegra241_cmdqv_probe(struct arm_smmu_device *smmu) 
	return ERR_PTR(-ENODEV);

}

#endif /* CONFIG_TEGRA241_CMDQV */



#if IS_ENABLED(CONFIG_ARM_SMMU_V3_IOMMUFD)

void *arm_smmu_hw_info(struct device *dev, u32 *length, u32 *type);

#else

#define arm_smmu_hw_info NULL

#endif /* CONFIG_ARM_SMMU_V3_IOMMUFD */



#endif /* _ARM_SMMU_V3_H */