Commit 69cb8998 authored by ChunHao Lin's avatar ChunHao Lin Committed by Jakub Kicinski
Browse files

r8169: add support for RTL8126A rev.b 



Add support for RTL8126A rev.b. Its XID is 0x64a. It is basically
based on the one with XID 0x649, but with different firmware file.

Signed-off-by: default avatarChunHao Lin <hau@realtek.com>
Reviewed-by: default avatarHeiner Kallweit <hkallweit1@gmail.com>
Link: https://patch.msgid.link/20240830021810.11993-1-hau@realtek.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 4e3a024b

drivers/net/ethernet/realtek/r8169.h

+1 −0
Original line number Diff line number Diff line
@@ -69,6 +69,7 @@ enum mac_version { 
	RTL_GIGA_MAC_VER_61,

	RTL_GIGA_MAC_VER_63,

	RTL_GIGA_MAC_VER_65,

	RTL_GIGA_MAC_VER_66,

	RTL_GIGA_MAC_NONE

};

drivers/net/ethernet/realtek/r8169_main.c

+27 −15
Original line number Diff line number Diff line
@@ -56,6 +56,7 @@ 
#define FIRMWARE_8125A_3	"rtl_nic/rtl8125a-3.fw"

#define FIRMWARE_8125B_2	"rtl_nic/rtl8125b-2.fw"

#define FIRMWARE_8126A_2	"rtl_nic/rtl8126a-2.fw"

#define FIRMWARE_8126A_3	"rtl_nic/rtl8126a-3.fw"



#define TX_DMA_BURST	7	/* Maximum PCI burst, '7' is unlimited */

#define InterFrameGap	0x03	/* 3 means InterFrameGap = the shortest one */
@@ -138,6 +139,7 @@ static const struct { 
	/* reserve 62 for CFG_METHOD_4 in the vendor driver */

	[RTL_GIGA_MAC_VER_63] = {"RTL8125B",		FIRMWARE_8125B_2},

	[RTL_GIGA_MAC_VER_65] = {"RTL8126A",		FIRMWARE_8126A_2},

	[RTL_GIGA_MAC_VER_66] = {"RTL8126A",		FIRMWARE_8126A_3},

};



static const struct pci_device_id rtl8169_pci_tbl[] = {
@@ -1201,7 +1203,7 @@ static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 
	case RTL_GIGA_MAC_VER_31:

		r8168dp_2_mdio_write(tp, location, val);

		break;

	case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65:

	case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66:

		r8168g_mdio_write(tp, location, val);

		break;

	default:
@@ -1216,7 +1218,7 @@ static int rtl_readphy(struct rtl8169_private *tp, int location) 
	case RTL_GIGA_MAC_VER_28:

	case RTL_GIGA_MAC_VER_31:

		return r8168dp_2_mdio_read(tp, location);

	case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65:

	case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66:

		return r8168g_mdio_read(tp, location);

	default:

		return r8169_mdio_read(tp, location);
@@ -1425,7 +1427,7 @@ static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable) 
	case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26:

	case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30:

	case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37:

	case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_65:

	case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_66:

		if (enable)

			RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN);

		else
@@ -1592,7 +1594,7 @@ static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 
		break;

	case RTL_GIGA_MAC_VER_34:

	case RTL_GIGA_MAC_VER_37:

	case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_65:

	case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_66:

		if (wolopts)

			rtl_mod_config2(tp, 0, PME_SIGNAL);

		else
@@ -2071,6 +2073,7 @@ static void rtl_set_eee_txidle_timer(struct rtl8169_private *tp) 
	case RTL_GIGA_MAC_VER_61:

	case RTL_GIGA_MAC_VER_63:

	case RTL_GIGA_MAC_VER_65:

	case RTL_GIGA_MAC_VER_66:

		tp->tx_lpi_timer = timer_val;

		RTL_W16(tp, EEE_TXIDLE_TIMER_8125, timer_val);

		break;
@@ -2199,6 +2202,7 @@ static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) 
		enum mac_version ver;

	} mac_info[] = {

		/* 8126A family. */

		{ 0x7cf, 0x64a,	RTL_GIGA_MAC_VER_66 },

		{ 0x7cf, 0x649,	RTL_GIGA_MAC_VER_65 },



		/* 8125B family. */
@@ -2470,6 +2474,7 @@ static void rtl_init_rxcfg(struct rtl8169_private *tp) 
		break;

	case RTL_GIGA_MAC_VER_63:

	case RTL_GIGA_MAC_VER_65:

	case RTL_GIGA_MAC_VER_66:

		RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST |

			RX_PAUSE_SLOT_ON);

		break;
@@ -2656,7 +2661,7 @@ static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) 
	case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61:

		rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);

		break;

	case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_65:

	case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_66:

		RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);

		rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);

		rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42);
@@ -2899,7 +2904,7 @@ static void rtl_enable_exit_l1(struct rtl8169_private *tp) 
	case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38:

		rtl_eri_set_bits(tp, 0xd4, 0x0c00);

		break;

	case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65:

	case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66:

		r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80);

		break;

	default:
@@ -2913,7 +2918,7 @@ static void rtl_disable_exit_l1(struct rtl8169_private *tp) 
	case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:

		rtl_eri_clear_bits(tp, 0xd4, 0x1f00);

		break;

	case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65:

	case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66:

		r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0);

		break;

	default:
@@ -2940,6 +2945,7 @@ static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 
		rtl_mod_config5(tp, 0, ASPM_en);

		switch (tp->mac_version) {

		case RTL_GIGA_MAC_VER_65:

		case RTL_GIGA_MAC_VER_66:

			val8 = RTL_R8(tp, INT_CFG0_8125) | INT_CFG0_CLKREQEN;

			RTL_W8(tp, INT_CFG0_8125, val8);

			break;
@@ -2950,7 +2956,7 @@ static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 


		switch (tp->mac_version) {

		case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:

		case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65:

		case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66:

			/* reset ephy tx/rx disable timer */

			r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0);

			/* chip can trigger L1.2 */
@@ -2962,7 +2968,7 @@ static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 
	} else {

		switch (tp->mac_version) {

		case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:

		case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65:

		case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66:

			r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0);

			break;

		default:
@@ -2971,6 +2977,7 @@ static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 


		switch (tp->mac_version) {

		case RTL_GIGA_MAC_VER_65:

		case RTL_GIGA_MAC_VER_66:

			val8 = RTL_R8(tp, INT_CFG0_8125) & ~INT_CFG0_CLKREQEN;

			RTL_W8(tp, INT_CFG0_8125, val8);

			break;
@@ -3690,10 +3697,12 @@ static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 
	/* disable new tx descriptor format */

	r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);



	if (tp->mac_version == RTL_GIGA_MAC_VER_65)

	if (tp->mac_version == RTL_GIGA_MAC_VER_65 ||

	    tp->mac_version == RTL_GIGA_MAC_VER_66)

		RTL_W8(tp, 0xD8, RTL_R8(tp, 0xD8) & ~0x02);



	if (tp->mac_version == RTL_GIGA_MAC_VER_65)

	if (tp->mac_version == RTL_GIGA_MAC_VER_65 ||

	    tp->mac_version == RTL_GIGA_MAC_VER_66)

		r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);

	else if (tp->mac_version == RTL_GIGA_MAC_VER_63)

		r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200);
@@ -3711,7 +3720,8 @@ static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 
	r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);

	r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);

	r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001);

	if (tp->mac_version == RTL_GIGA_MAC_VER_65)

	if (tp->mac_version == RTL_GIGA_MAC_VER_65 ||

	    tp->mac_version == RTL_GIGA_MAC_VER_66)

		r8168_mac_ocp_modify(tp, 0xea1c, 0x0300, 0x0000);

	else

		r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
@@ -3825,6 +3835,7 @@ static void rtl_hw_config(struct rtl8169_private *tp) 
		[RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2,

		[RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b,

		[RTL_GIGA_MAC_VER_65] = rtl_hw_start_8126a,

		[RTL_GIGA_MAC_VER_66] = rtl_hw_start_8126a,

	};



	if (hw_configs[tp->mac_version])
@@ -3845,6 +3856,7 @@ static void rtl_hw_start_8125(struct rtl8169_private *tp) 
		break;

	case RTL_GIGA_MAC_VER_63:

	case RTL_GIGA_MAC_VER_65:

	case RTL_GIGA_MAC_VER_66:

		for (i = 0xa00; i < 0xa80; i += 4)

			RTL_W32(tp, i, 0);

		RTL_W16(tp, INT_CFG1_8125, 0x0000);
@@ -4073,7 +4085,7 @@ static void rtl8169_cleanup(struct rtl8169_private *tp) 
		RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);

		rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);

		break;

	case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65:

	case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66:

		rtl_enable_rxdvgate(tp);

		fsleep(2000);

		break;
@@ -4224,7 +4236,7 @@ static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp, 


	switch (tp->mac_version) {

	case RTL_GIGA_MAC_VER_34:

	case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65:

	case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66:

		padto = max_t(unsigned int, padto, ETH_ZLEN);

		break;

	default:
@@ -5257,7 +5269,7 @@ static void rtl_hw_initialize(struct rtl8169_private *tp) 
	case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:

		rtl_hw_init_8168g(tp);

		break;

	case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65:

	case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66:

		rtl_hw_init_8125(tp);

		break;

	default:

drivers/net/ethernet/realtek/r8169_phy_config.c

+1 −0
Original line number Diff line number Diff line
@@ -1159,6 +1159,7 @@ void r8169_hw_phy_config(struct rtl8169_private *tp, struct phy_device *phydev, 
		[RTL_GIGA_MAC_VER_61] = rtl8125a_2_hw_phy_config,

		[RTL_GIGA_MAC_VER_63] = rtl8125b_hw_phy_config,

		[RTL_GIGA_MAC_VER_65] = rtl8126a_hw_phy_config,

		[RTL_GIGA_MAC_VER_66] = rtl8126a_hw_phy_config,

	};



	if (phy_configs[ver])