Commit 6a1fd678 authored by Tejas Upadhyay's avatar Tejas Upadhyay Committed by Rodrigo Vivi
Browse files

drm/xe/xe2: Add workaround 14019988906 



This workaround applies to Graphics 20.04 as engine
workaround

V2(MattR):
 - Reorder bit define
 - Apply WA for RCS only

Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarTejas Upadhyay <tejas.upadhyay@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent d8b15713

drivers/gpu/drm/xe/regs/xe_gt_regs.h

+1 −0
Original line number Diff line number Diff line
@@ -124,6 +124,7 @@ 
#define   SCOREBOARD_STALL_FLUSH_CONTROL	REG_BIT(5)



#define XEHP_PSS_CHICKEN			XE_REG_MCR(0x7044, XE_REG_OPTION_MASKED)

#define   FLSH_IGNORES_PSD			REG_BIT(10)

#define   FD_END_COLLECT			REG_BIT(5)



#define HIZ_CHICKEN					XE_REG(0x7018, XE_REG_OPTION_MASKED)

drivers/gpu/drm/xe/xe_wa.c

+4 −0
Original line number Diff line number Diff line
@@ -719,6 +719,10 @@ static const struct xe_rtp_entry_sr lrc_was[] = { 
		       ENGINE_CLASS(RENDER)),

	  XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS))

	},

	{ XE_RTP_NAME("14019988906"),

	  XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),

	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))

	},



	{}

};