Commit 6ba5b613 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu: add a module parameter to control the AGP aperture 



Add a module parameter to control the AGP aperture.  The AGP
aperture is an aperture in the GPU's internal address space
which provides direct non-paged access to the platform address
space.  This access is non-snooped so only uncached memory
can be accessed.

Add a knob so that we can toggle this for debugging.

Fixes: 67318cb8 ("drm/amdgpu/gmc11: set gart placement GC11")
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarMario Limonciello <mario.limonciello@amd.com>
Tested-by: Mario Limonciello <mario.limonciello@amd.com> # PHX & Navi33
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 564ca1b5

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+1 −0
Original line number Diff line number Diff line
@@ -248,6 +248,7 @@ extern int amdgpu_umsch_mm; 
extern int amdgpu_seamless;



extern int amdgpu_user_partt_mode;

extern int amdgpu_agp;



#define AMDGPU_VM_MAX_NUM_CTX			4096

#define AMDGPU_SG_THRESHOLD			(256*1024*1024)

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+10 −0
Original line number Diff line number Diff line
@@ -207,6 +207,7 @@ int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE; 
int amdgpu_umsch_mm;

int amdgpu_seamless = -1; /* auto */

uint amdgpu_debug_mask;

int amdgpu_agp = -1; /* auto */



static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work);
@@ -961,6 +962,15 @@ module_param_named(seamless, amdgpu_seamless, int, 0444); 
MODULE_PARM_DESC(debug_mask, "debug options for amdgpu, disabled by default");

module_param_named(debug_mask, amdgpu_debug_mask, uint, 0444);



/**

 * DOC: agp (int)

 * Enable the AGP aperture.  This provides an aperture in the GPU's internal

 * address space for direct access to system memory.  Note that these accesses

 * are non-snooped, so they are only used for access to uncached memory.

 */

MODULE_PARM_DESC(agp, "AGP (-1 = auto (default), 0 = disable, 1 = enable)");

module_param_named(agp, amdgpu_agp, int, 0444);



/* These devices are not supported by amdgpu.

 * They are supported by the mach64, r128, radeon drivers

 */

drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c

+1 −1
Original line number Diff line number Diff line
@@ -675,7 +675,7 @@ static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev, 
	amdgpu_gmc_set_agp_default(adev, mc);

	amdgpu_gmc_vram_location(adev, &adev->gmc, base);

	amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT);

	if (!amdgpu_sriov_vf(adev))

	if (!amdgpu_sriov_vf(adev) && (amdgpu_agp != 0))

		amdgpu_gmc_agp_location(adev, mc);



	/* base offset of vram pages */

drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c

+2 −1
Original line number Diff line number Diff line
@@ -641,7 +641,8 @@ static void gmc_v11_0_vram_gtt_location(struct amdgpu_device *adev, 
	amdgpu_gmc_vram_location(adev, &adev->gmc, base);

	amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_HIGH);

	if (!amdgpu_sriov_vf(adev) &&

	    (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(11, 5, 0)))

	    (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(11, 5, 0)) &&

	    (amdgpu_agp != 0))

		amdgpu_gmc_agp_location(adev, mc);



	/* base offset of vram pages */

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

+1 −1
Original line number Diff line number Diff line
@@ -1630,7 +1630,7 @@ static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, 
	} else {

		amdgpu_gmc_vram_location(adev, mc, base);

		amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT);

		if (!amdgpu_sriov_vf(adev))

		if (!amdgpu_sriov_vf(adev) && (amdgpu_agp != 0))

			amdgpu_gmc_agp_location(adev, mc);

	}

	/* base offset of vram pages */