Commit 6bba2d3f authored by Bard Liao's avatar Bard Liao Committed by Vinod Koul
Browse files

soundwire: add lane field in sdw_port_runtime



Currently, lane_ctrl is always 0. Add a lane field in sdw_port_runtime
to indicate the data lane of the data port.
They are 0 by default.

Signed-off-by: default avatarBard Liao <yung-chuan.liao@linux.intel.com>
Link: https://lore.kernel.org/r/20241218080155.102405-2-yung-chuan.liao@linux.intel.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent a5fef9ba
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+1 −1
Original line number Diff line number Diff line
@@ -410,7 +410,7 @@ static int amd_sdw_compute_params(struct sdw_bus *bus)
			sdw_fill_xport_params(&p_rt->transport_params, p_rt->num,
					      false, SDW_BLK_GRP_CNT_1, sample_int,
					      port_bo, port_bo >> 8, hstart, hstop,
					      SDW_BLK_PKG_PER_PORT, 0x0);
					      SDW_BLK_PKG_PER_PORT, p_rt->lane);

			sdw_fill_port_params(&p_rt->port_params,
					     p_rt->num, bps,
+2 −0
Original line number Diff line number Diff line
@@ -90,6 +90,7 @@ int sdw_find_col_index(int col);
 * @transport_params: Transport parameters
 * @port_params: Port parameters
 * @port_node: List node for Master or Slave port_list
 * @lane: Which lane is used
 *
 * SoundWire spec has no mention of ports for Master interface but the
 * concept is logically extended.
@@ -100,6 +101,7 @@ struct sdw_port_runtime {
	struct sdw_transport_params transport_params;
	struct sdw_port_params port_params;
	struct list_head port_node;
	unsigned int lane;
};

/**
+2 −2
Original line number Diff line number Diff line
@@ -56,7 +56,7 @@ void sdw_compute_slave_ports(struct sdw_master_runtime *m_rt,
					      sample_int, port_bo, port_bo >> 8,
					      t_data->hstart,
					      t_data->hstop,
					      SDW_BLK_PKG_PER_PORT, 0x0);
					      SDW_BLK_PKG_PER_PORT, p_rt->lane);

			sdw_fill_port_params(&p_rt->port_params,
					     p_rt->num, bps,
@@ -109,7 +109,7 @@ static void sdw_compute_master_ports(struct sdw_master_runtime *m_rt,
		sdw_fill_xport_params(&p_rt->transport_params, p_rt->num,
				      false, SDW_BLK_GRP_CNT_1, sample_int,
				      *port_bo, (*port_bo) >> 8, hstart, hstop,
				      SDW_BLK_PKG_PER_PORT, 0x0);
				      SDW_BLK_PKG_PER_PORT, p_rt->lane);

		sdw_fill_port_params(&p_rt->port_params,
				     p_rt->num, bps,