Commit 6bd8b0bc authored by Duy Nguyen's avatar Duy Nguyen Committed by Geert Uytterhoeven
Browse files

arm64: dts: renesas: r8a779h0: Add CA76 operating points 



Add operating points for running the Cortex-A76 CPU cores on R-Car V4M
at various speeds, up to the Normal (1.0 GHz).

Signed-off-by: default avatarDuy Nguyen <duy.nguyen.rh@renesas.com>
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/736b5836ec2b54e8b36712866309dc1b7ee1fc48.1706796979.git.geert+renesas@glider.be
parent 4c1fd23a

arch/arm64/boot/dts/renesas/r8a779h0.dtsi

+20 −0
Original line number Diff line number Diff line
@@ -14,6 +14,22 @@ / { 
	#address-cells = <2>;

	#size-cells = <2>;



	cluster0_opp: opp-table-0 {

		compatible = "operating-points-v2";

		opp-shared;



		opp-500000000 {

			opp-hz = /bits/ 64 <500000000>;

			opp-microvolt = <825000>;

			clock-latency-ns = <500000>;

		};

		opp-1000000000 {

			opp-hz = /bits/ 64 <1000000000>;

			opp-microvolt = <825000>;

			clock-latency-ns = <500000>;

		};

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;
@@ -44,6 +60,7 @@ a76_0: cpu@0 { 
			enable-method = "psci";

			cpu-idle-states = <&CPU_SLEEP_0>;

			clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC0>;

			operating-points-v2 = <&cluster0_opp>;

		};



		a76_1: cpu@100 {
@@ -55,6 +72,7 @@ a76_1: cpu@100 { 
			enable-method = "psci";

			cpu-idle-states = <&CPU_SLEEP_0>;

			clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC1>;

			operating-points-v2 = <&cluster0_opp>;

		};



		a76_2: cpu@200 {
@@ -66,6 +84,7 @@ a76_2: cpu@200 { 
			enable-method = "psci";

			cpu-idle-states = <&CPU_SLEEP_0>;

			clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC2>;

			operating-points-v2 = <&cluster0_opp>;

		};



		a76_3: cpu@300 {
@@ -77,6 +96,7 @@ a76_3: cpu@300 { 
			enable-method = "psci";

			cpu-idle-states = <&CPU_SLEEP_0>;

			clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC3>;

			operating-points-v2 = <&cluster0_opp>;

		};



		idle-states {