Commit 6be146cf authored by Simona Vetter's avatar Simona Vetter
Browse files

Merge tag 'amd-drm-next-6.11-2024-07-03' of... 

Merge tag 'amd-drm-next-6.11-2024-07-03' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-next

amd-drm-next-6.11-2024-07-03:

amdgpu:
- Use vmalloc for dc_state
- Replay fixes
- Freesync fixes
- DCN 4.0.1 fixes
- DML fixes
- DCC updates
- Misc code cleanups and bug fixes
- 8K display fixes
- DCN 3.5 fixes
- Restructure DIO code
- DML1 fixes
- DML2 fixes
- GFX11 fix
- GFX12 updates
- GFX12 modifiers fixes
- RAS fixes
- IP dump fixes
- Add some updated IP version checks
_ Silence UBSAN warning

radeon:
- GPUVM fix

Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240703211314.2041893-1-alexander.deucher@amd.com
parents 71e9f407 4ed6a368

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

+11 −0
Original line number Diff line number Diff line
@@ -1808,6 +1808,7 @@ static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev) 
	case IP_VERSION(11, 0, 4):

	case IP_VERSION(11, 5, 0):

	case IP_VERSION(11, 5, 1):

	case IP_VERSION(11, 5, 2):

		amdgpu_device_ip_block_add(adev, &soc21_common_ip_block);

		break;

	case IP_VERSION(12, 0, 0):
@@ -1861,6 +1862,7 @@ static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev) 
	case IP_VERSION(11, 0, 4):

	case IP_VERSION(11, 5, 0):

	case IP_VERSION(11, 5, 1):

	case IP_VERSION(11, 5, 2):

		amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block);

		break;

	case IP_VERSION(12, 0, 0):
@@ -1962,6 +1964,7 @@ static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) 
	case IP_VERSION(13, 0, 14):

	case IP_VERSION(14, 0, 0):

	case IP_VERSION(14, 0, 1):

	case IP_VERSION(14, 0, 4):

		amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);

		break;

	case IP_VERSION(13, 0, 4):
@@ -2025,6 +2028,7 @@ static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev) 
	case IP_VERSION(14, 0, 1):

	case IP_VERSION(14, 0, 2):

	case IP_VERSION(14, 0, 3):

	case IP_VERSION(14, 0, 4):

		amdgpu_device_ip_block_add(adev, &smu_v14_0_ip_block);

		break;

	default:
@@ -2152,6 +2156,7 @@ static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) 
	case IP_VERSION(11, 0, 4):

	case IP_VERSION(11, 5, 0):

	case IP_VERSION(11, 5, 1):

	case IP_VERSION(11, 5, 2):

		amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block);

		break;

	case IP_VERSION(12, 0, 0):
@@ -2207,6 +2212,7 @@ static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev) 
	case IP_VERSION(6, 0, 3):

	case IP_VERSION(6, 1, 0):

	case IP_VERSION(6, 1, 1):

	case IP_VERSION(6, 1, 2):

		amdgpu_device_ip_block_add(adev, &sdma_v6_0_ip_block);

		break;

	case IP_VERSION(7, 0, 0):
@@ -2325,6 +2331,7 @@ static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) 
	case IP_VERSION(11, 0, 4):

	case IP_VERSION(11, 5, 0):

	case IP_VERSION(11, 5, 1):

	case IP_VERSION(11, 5, 2):

		amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block);

		adev->enable_mes = true;

		adev->enable_mes_kiq = true;
@@ -2360,6 +2367,7 @@ static int amdgpu_discovery_set_vpe_ip_blocks(struct amdgpu_device *adev) 
	switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) {

	case IP_VERSION(6, 1, 0):

	case IP_VERSION(6, 1, 1):

	case IP_VERSION(6, 1, 3):

		amdgpu_device_ip_block_add(adev, &vpe_v6_1_ip_block);

		break;

	default:
@@ -2634,6 +2642,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 
		break;

	case IP_VERSION(11, 5, 0):

	case IP_VERSION(11, 5, 1):

	case IP_VERSION(11, 5, 2):

		adev->family = AMDGPU_FAMILY_GC_11_5_0;

		break;

	case IP_VERSION(12, 0, 0):
@@ -2658,6 +2667,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 
	case IP_VERSION(11, 0, 4):

	case IP_VERSION(11, 5, 0):

	case IP_VERSION(11, 5, 1):

	case IP_VERSION(11, 5, 2):

		adev->flags |= AMD_IS_APU;

		break;

	default:
@@ -2696,6 +2706,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 
		break;

	case IP_VERSION(7, 11, 0):

	case IP_VERSION(7, 11, 1):

	case IP_VERSION(7, 11, 3):

		adev->nbio.funcs = &nbio_v7_11_funcs;

		adev->nbio.hdp_flush_reg = &nbio_v7_11_hdp_flush_reg;

		break;

drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

+57 −37
Original line number Diff line number Diff line
@@ -654,6 +654,10 @@ amdgpu_lookup_format_info(u32 format, uint64_t modifier) 
	if (!IS_AMD_FMT_MOD(modifier))

		return NULL;



	if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) < AMD_FMT_MOD_TILE_VER_GFX9 ||

	    AMD_FMT_MOD_GET(TILE_VERSION, modifier) >= AMD_FMT_MOD_TILE_VER_GFX12)

		return NULL;



	if (AMD_FMT_MOD_GET(DCC_RETILE, modifier))

		return lookup_format_info(dcc_retile_formats,

					  ARRAY_SIZE(dcc_retile_formats),
@@ -720,32 +724,25 @@ extract_render_dcc_offset(struct amdgpu_device *adev, 


static int convert_tiling_flags_to_modifier_gfx12(struct amdgpu_framebuffer *afb)

{

	struct amdgpu_device *adev = drm_to_adev(afb->base.dev);

	const struct drm_format_info *format_info;

	u64 modifier = 0;

	int tile = 0;

	int swizzle = 0;

	int swizzle_mode = AMDGPU_TILING_GET(afb->tiling_flags, GFX12_SWIZZLE_MODE);



	if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) {

		tile = AMD_FMT_MOD_TILE_VER_GFX12;

		swizzle =  AMDGPU_TILING_GET(afb->tiling_flags, GFX12_SWIZZLE_MODE);

	}

	if (!swizzle_mode) {

		modifier = DRM_FORMAT_MOD_LINEAR;

	} else {

		int max_comp_block =

			AMDGPU_TILING_GET(afb->tiling_flags, GFX12_DCC_MAX_COMPRESSED_BLOCK);



		modifier =

			AMD_FMT_MOD |

		AMD_FMT_MOD_SET(TILE, swizzle) |

		AMD_FMT_MOD_SET(TILE_VERSION,  tile) |

		AMD_FMT_MOD_SET(DCC, 0) |

		AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, 0);



	format_info = amdgpu_lookup_format_info(afb->base.format->format,

						modifier);

	if (!format_info)

		return -EINVAL;

			AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX12) |

			AMD_FMT_MOD_SET(TILE, swizzle_mode) |

			AMD_FMT_MOD_SET(DCC, afb->gfx12_dcc) |

			AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, max_comp_block);

	}



	afb->base.modifier = modifier;

	afb->base.flags |= DRM_MODE_FB_MODIFIERS;



	return 0;

}
@@ -773,12 +770,6 @@ static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb) 
		int pipes = ilog2(num_pipes);

		uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B);





		if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) {

			convert_tiling_flags_to_modifier_gfx12(afb);

			return 0;

		}



		switch (swizzle >> 2) {

		case 0: /* 256B */

			block_size_bits = 8;
@@ -954,8 +945,7 @@ static int check_tiling_flags_gfx6(struct amdgpu_framebuffer *afb) 
{

	u64 micro_tile_mode;



	/* Zero swizzle mode means linear */

	if (AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0)

	if (AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) == 1) /* LINEAR_ALIGNED */

		return 0;



	micro_tile_mode = AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE);
@@ -1079,6 +1069,30 @@ static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb) 
			block_width = 256 / format_info->cpp[i];

			block_height = 1;

			block_size_log2 = 8;

		} else if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) >= AMD_FMT_MOD_TILE_VER_GFX12) {

			int swizzle = AMD_FMT_MOD_GET(TILE, modifier);



			switch (swizzle) {

			case AMD_FMT_MOD_TILE_GFX12_256B_2D:

				block_size_log2 = 8;

				break;

			case AMD_FMT_MOD_TILE_GFX12_4K_2D:

				block_size_log2 = 12;

				break;

			case AMD_FMT_MOD_TILE_GFX12_64K_2D:

				block_size_log2 = 16;

				break;

			case AMD_FMT_MOD_TILE_GFX12_256K_2D:

				block_size_log2 = 18;

				break;

			default:

				drm_dbg_kms(rfb->base.dev,

					    "Gfx12 swizzle mode with unknown block size: %d\n", swizzle);

				return -EINVAL;

			}



			get_block_dimensions(block_size_log2, format_info->cpp[i],

					     &block_width, &block_height);

		} else {

			int swizzle = AMD_FMT_MOD_GET(TILE, modifier);
@@ -1114,7 +1128,8 @@ static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb) 
			return ret;

	}



	if (AMD_FMT_MOD_GET(DCC, modifier)) {

	if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) <= AMD_FMT_MOD_TILE_VER_GFX11 &&

	    AMD_FMT_MOD_GET(DCC, modifier)) {

		if (AMD_FMT_MOD_GET(DCC_RETILE, modifier)) {

			block_size_log2 = get_dcc_block_size(modifier, false, false);

			get_block_dimensions(block_size_log2 + 8, format_info->cpp[0],
@@ -1144,7 +1159,8 @@ static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb) 
}



static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,

				      uint64_t *tiling_flags, bool *tmz_surface)

				      uint64_t *tiling_flags, bool *tmz_surface,

				      bool *gfx12_dcc)

{

	struct amdgpu_bo *rbo;

	int r;
@@ -1152,6 +1168,7 @@ static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb 
	if (!amdgpu_fb) {

		*tiling_flags = 0;

		*tmz_surface = false;

		*gfx12_dcc = false;

		return 0;

	}
@@ -1165,11 +1182,9 @@ static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb 
		return r;

	}



	if (tiling_flags)

	amdgpu_bo_get_tiling_flags(rbo, tiling_flags);



	if (tmz_surface)

	*tmz_surface = amdgpu_bo_encrypted(rbo);

	*gfx12_dcc = rbo->flags & AMDGPU_GEM_CREATE_GFX12_DCC;



	amdgpu_bo_unreserve(rbo);
@@ -1238,7 +1253,8 @@ static int amdgpu_display_framebuffer_init(struct drm_device *dev, 
		}

	}



	ret = amdgpu_display_get_fb_info(rfb, &rfb->tiling_flags, &rfb->tmz_surface);

	ret = amdgpu_display_get_fb_info(rfb, &rfb->tiling_flags, &rfb->tmz_surface,

					 &rfb->gfx12_dcc);

	if (ret)

		return ret;
@@ -1252,7 +1268,11 @@ static int amdgpu_display_framebuffer_init(struct drm_device *dev, 


	if (!dev->mode_config.fb_modifiers_not_supported &&

	    !(rfb->base.flags & DRM_MODE_FB_MODIFIERS)) {

		if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 0, 0))

			ret = convert_tiling_flags_to_modifier_gfx12(rfb);

		else

			ret = convert_tiling_flags_to_modifier(rfb);



		if (ret) {

			drm_dbg_kms(dev, "Failed to convert tiling flags 0x%llX to a modifier",

				    rfb->tiling_flags);

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c

+1 −0
Original line number Diff line number Diff line
@@ -848,6 +848,7 @@ void amdgpu_gmc_tmz_set(struct amdgpu_device *adev) 
	case IP_VERSION(11, 0, 4):

	case IP_VERSION(11, 5, 0):

	case IP_VERSION(11, 5, 1):

	case IP_VERSION(11, 5, 2):

		/* Don't enable it by default yet.

		 */

		if (amdgpu_tmz < 1) {

drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h

+1 −0
Original line number Diff line number Diff line
@@ -300,6 +300,7 @@ struct amdgpu_framebuffer { 


	uint64_t tiling_flags;

	bool tmz_surface;

	bool gfx12_dcc;



	/* caching for later use */

	uint64_t address;

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

+1 −0
Original line number Diff line number Diff line
@@ -219,6 +219,7 @@ static int psp_early_init(void *handle) 
	case IP_VERSION(13, 0, 11):

	case IP_VERSION(14, 0, 0):

	case IP_VERSION(14, 0, 1):

	case IP_VERSION(14, 0, 4):

		psp_v13_0_set_psp_funcs(psp);

		psp->boot_time_tmr = false;

		break;