Unverified Commit 6c1d134a authored by Rafał Miłecki's avatar Rafał Miłecki Committed by AngeloGioacchino Del Regno
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arm64: dts: mediatek: Add initial MT7988A and BPI-R4 



MT7988A (AKA MediaTek Filogic 880) is a quad-core ARM Cortex-A73
platform designed for Wi-Fi 7 devices (there is no wireless on SoC
though). The first public MT7988A device is Banana Pi BPI-R4.

Many SoC parts remain to be added (they need their own bindings or
depend on missing clocks). Those present block however are correct and
having base .dtsi will help testing & working on missing stuff.

Signed-off-by: default avatarRafał Miłecki <rafal@milecki.pl>
Link: https://lore.kernel.org/r/20240108085228.4727-3-zajec5@gmail.com


Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
parent 1e136f4a

arch/arm64/boot/dts/mediatek/Makefile

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@@ -16,6 +16,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nor.dtbo 
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd.dtbo

dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb

arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts

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// SPDX-License-Identifier: GPL-2.0-only OR MIT



/dts-v1/;



#include "mt7988a.dtsi"



/ {

	compatible = "bananapi,bpi-r4", "mediatek,mt7988a";

	model = "Banana Pi BPI-R4";

	chassis-type = "embedded";

};

arch/arm64/boot/dts/mediatek/mt7988a.dtsi

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// SPDX-License-Identifier: GPL-2.0-only OR MIT



#include <dt-bindings/interrupt-controller/arm-gic.h>



/ {

	compatible = "mediatek,mt7988a";

	interrupt-parent = <&gic>;

	#address-cells = <2>;

	#size-cells = <2>;



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu@0 {

			compatible = "arm,cortex-a73";

			reg = <0x0>;

			device_type = "cpu";

			enable-method = "psci";

		};



		cpu@1 {

			compatible = "arm,cortex-a73";

			reg = <0x1>;

			device_type = "cpu";

			enable-method = "psci";

		};



		cpu@2 {

			compatible = "arm,cortex-a73";

			reg = <0x2>;

			device_type = "cpu";

			enable-method = "psci";

		};



		cpu@3 {

			compatible = "arm,cortex-a73";

			reg = <0x3>;

			device_type = "cpu";

			enable-method = "psci";

		};

	};



	oscillator-40m {

		compatible = "fixed-clock";

		clock-frequency = <40000000>;

		#clock-cells = <0>;

		clock-output-names = "clkxtal";

	};



	pmu {

		compatible = "arm,cortex-a73-pmu";

		interrupt-parent = <&gic>;

		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;

	};



	psci {

		compatible = "arm,psci-0.2";

		method = "smc";

	};



	soc {

		compatible = "simple-bus";

		ranges;

		#address-cells = <2>;

		#size-cells = <2>;



		gic: interrupt-controller@c000000 {

			compatible = "arm,gic-v3";

			reg = <0 0x0c000000 0 0x40000>,  /* GICD */

			      <0 0x0c080000 0 0x200000>, /* GICR */

			      <0 0x0c400000 0 0x2000>,   /* GICC */

			      <0 0x0c410000 0 0x1000>,   /* GICH */

			      <0 0x0c420000 0 0x2000>;   /* GICV */

			interrupt-parent = <&gic>;

			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-controller;

			#interrupt-cells = <3>;

		};



		watchdog@1001c000 {

			compatible = "mediatek,mt7988-wdt";

			reg = <0 0x1001c000 0 0x1000>;

			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;

			#reset-cells = <1>;

		};

	};



	timer {

		compatible = "arm,armv8-timer";

		interrupt-parent = <&gic>;

		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;

	};

};