Commit 6c6915bf authored by Anna Maniscalco's avatar Anna Maniscalco Committed by Rob Clark
Browse files

drm/msm: add PERFCTR_CNTL to ifpc_reglist 



Previously this register would become 0 after IFPC took place which
broke all usages of counters.

Fixes: a6a0157c ("drm/msm/a6xx: Enable IFPC on Adreno X1-85")
Cc: stable@vger.kernel.org
Signed-off-by: default avatarAnna Maniscalco <anna.maniscalco2000@gmail.com>
Reviewed-by: default avatarAkhil P Oommen <akhilpo@oss.qualcomm.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/690960/


Message-ID: <20251127-ifpc_counters-v3-1-fac0a126bc88@gmail.com>
Signed-off-by: default avatarRob Clark <robin.clark@oss.qualcomm.com>
parent ef3b0409

drivers/gpu/drm/msm/adreno/a6xx_catalog.c

+1 −0
Original line number Diff line number Diff line
@@ -1392,6 +1392,7 @@ static const u32 a750_ifpc_reglist_regs[] = { 
	REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(2),

	REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(3),

	REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(4),

	REG_A6XX_RBBM_PERFCTR_CNTL,

	REG_A6XX_TPL1_NC_MODE_CNTL,

	REG_A6XX_SP_NC_MODE_CNTL,

	REG_A6XX_CP_DBG_ECO_CNTL,