Commit 6c8d1f4b authored by Jesse.zhang@amd.com's avatar Jesse.zhang@amd.com Committed by Alex Deucher
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drm/amdgpu: Add sysfs interface for gc reset mask 



Add two sysfs interfaces for gfx and compute:
gfx_reset_mask
compute_reset_mask

These interfaces are read-only and show the resets supported by the IP.
For example, full adapter reset (mode1/mode2/BACO/etc),
soft reset, queue reset, and pipe reset.

V2: the sysfs node returns a text string instead of some flags (Christian)
v3: add a generic helper which takes the ring as parameter
    and print the strings in the order they are applied (Christian)

    check amdgpu_gpu_recovery  before creating sysfs file itself,
    and initialize supported_reset_types in IP version files (Lijo)
v4: Fixing uninitialized variables (Tim)

Signed-off-by: default avatarJesse Zhang <Jesse.Zhang@amd.com>
Suggested-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarTim Huang <tim.huang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f4a3246a

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+8 −0
Original line number Diff line number Diff line
@@ -299,6 +299,12 @@ extern int amdgpu_wbrf; 
#define AMDGPU_RESET_VCE			(1 << 13)

#define AMDGPU_RESET_VCE1			(1 << 14)



/* reset mask */

#define AMDGPU_RESET_TYPE_FULL (1 << 0) /* full adapter reset, mode1/mode2/BACO/etc. */

#define AMDGPU_RESET_TYPE_SOFT_RESET (1 << 1) /* IP level soft reset */

#define AMDGPU_RESET_TYPE_PER_QUEUE (1 << 2) /* per queue */

#define AMDGPU_RESET_TYPE_PER_PIPE (1 << 3) /* per pipe */



/* max cursor sizes (in pixels) */

#define CIK_CURSOR_WIDTH 128

#define CIK_CURSOR_HEIGHT 128
@@ -1464,6 +1470,8 @@ struct dma_fence *amdgpu_device_get_gang(struct amdgpu_device *adev); 
struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev,

					    struct dma_fence *gang);

bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev);

ssize_t amdgpu_get_soft_full_reset_mask(struct amdgpu_ring *ring);

ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset);



/* atpx handler */

#if defined(CONFIG_VGA_SWITCHEROO)

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+44 −0
Original line number Diff line number Diff line
@@ -6715,3 +6715,47 @@ uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, 
	}

	return ret;

}



ssize_t amdgpu_get_soft_full_reset_mask(struct amdgpu_ring *ring)

{

	ssize_t size = 0;



	if (!ring || !ring->adev)

		return size;



	if (amdgpu_device_should_recover_gpu(ring->adev))

		size |= AMDGPU_RESET_TYPE_FULL;



	if (unlikely(!ring->adev->debug_disable_soft_recovery) &&

	    !amdgpu_sriov_vf(ring->adev) && ring->funcs->soft_recovery)

		size |= AMDGPU_RESET_TYPE_SOFT_RESET;



	return size;

}



ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset)

{

	ssize_t size = 0;



	if (supported_reset == 0) {

		size += sysfs_emit_at(buf, size, "unsupported");

		size += sysfs_emit_at(buf, size, "\n");

		return size;



	}



	if (supported_reset & AMDGPU_RESET_TYPE_SOFT_RESET)

		size += sysfs_emit_at(buf, size, "soft ");



	if (supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)

		size += sysfs_emit_at(buf, size, "queue ");



	if (supported_reset & AMDGPU_RESET_TYPE_PER_PIPE)

		size += sysfs_emit_at(buf, size, "pipe ");



	if (supported_reset & AMDGPU_RESET_TYPE_FULL)

		size += sysfs_emit_at(buf, size, "full ");



	size += sysfs_emit_at(buf, size, "\n");

	return size;

}

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

+70 −0
Original line number Diff line number Diff line
@@ -1588,6 +1588,32 @@ static ssize_t amdgpu_gfx_set_enforce_isolation(struct device *dev, 
	return count;

}



static ssize_t amdgpu_gfx_get_gfx_reset_mask(struct device *dev,

						struct device_attribute *attr,

						char *buf)

{

	struct drm_device *ddev = dev_get_drvdata(dev);

	struct amdgpu_device *adev = drm_to_adev(ddev);



	if (!adev)

		return -ENODEV;



	return amdgpu_show_reset_mask(buf, adev->gfx.gfx_supported_reset);

}



static ssize_t amdgpu_gfx_get_compute_reset_mask(struct device *dev,

						struct device_attribute *attr,

						char *buf)

{

	struct drm_device *ddev = dev_get_drvdata(dev);

	struct amdgpu_device *adev = drm_to_adev(ddev);



	if (!adev)

		return -ENODEV;



	return amdgpu_show_reset_mask(buf, adev->gfx.compute_supported_reset);

}



static DEVICE_ATTR(run_cleaner_shader, 0200,

		   NULL, amdgpu_gfx_set_run_cleaner_shader);
@@ -1601,6 +1627,11 @@ static DEVICE_ATTR(current_compute_partition, 0644, 


static DEVICE_ATTR(available_compute_partition, 0444,

		   amdgpu_gfx_get_available_compute_partition, NULL);

static DEVICE_ATTR(gfx_reset_mask, 0444,

		   amdgpu_gfx_get_gfx_reset_mask, NULL);



static DEVICE_ATTR(compute_reset_mask, 0444,

		   amdgpu_gfx_get_compute_reset_mask, NULL);



static int amdgpu_gfx_sysfs_xcp_init(struct amdgpu_device *adev)

{
@@ -1666,6 +1697,40 @@ static void amdgpu_gfx_sysfs_isolation_shader_fini(struct amdgpu_device *adev) 
		device_remove_file(adev->dev, &dev_attr_run_cleaner_shader);

}



static int amdgpu_gfx_sysfs_reset_mask_init(struct amdgpu_device *adev)

{

	int r = 0;



	if (!amdgpu_gpu_recovery)

		return r;



	if (adev->gfx.num_gfx_rings) {

		r = device_create_file(adev->dev, &dev_attr_gfx_reset_mask);

		if (r)

			return r;

	}



	if (adev->gfx.num_compute_rings) {

		r = device_create_file(adev->dev, &dev_attr_compute_reset_mask);

		if (r)

			return r;

	}



	return r;

}



static void amdgpu_gfx_sysfs_reset_mask_fini(struct amdgpu_device *adev)

{

	if (!amdgpu_gpu_recovery)

		return;



	if (adev->gfx.num_gfx_rings)

		device_remove_file(adev->dev, &dev_attr_gfx_reset_mask);



	if (adev->gfx.num_compute_rings)

		device_remove_file(adev->dev, &dev_attr_compute_reset_mask);

}



int amdgpu_gfx_sysfs_init(struct amdgpu_device *adev)

{

	int r;
@@ -1680,6 +1745,10 @@ int amdgpu_gfx_sysfs_init(struct amdgpu_device *adev) 
	if (r)

		dev_err(adev->dev, "failed to create isolation sysfs files");



	r = amdgpu_gfx_sysfs_reset_mask_init(adev);

	if (r)

		dev_err(adev->dev, "failed to create reset mask sysfs files");



	return r;

}
@@ -1687,6 +1756,7 @@ void amdgpu_gfx_sysfs_fini(struct amdgpu_device *adev) 
{

	amdgpu_gfx_sysfs_xcp_fini(adev);

	amdgpu_gfx_sysfs_isolation_shader_fini(adev);

	amdgpu_gfx_sysfs_reset_mask_fini(adev);

}



int amdgpu_gfx_cleaner_shader_sw_init(struct amdgpu_device *adev,

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h

+2 −0
Original line number Diff line number Diff line
@@ -424,6 +424,8 @@ struct amdgpu_gfx { 
	/* reset mask */

	uint32_t                        grbm_soft_reset;

	uint32_t                        srbm_soft_reset;

	uint32_t 			gfx_supported_reset;

	uint32_t 			compute_supported_reset;



	/* gfx off */

	bool                            gfx_off_state;      /* true: enabled, false: disabled */

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+5 −0
Original line number Diff line number Diff line
@@ -4825,6 +4825,11 @@ static int gfx_v10_0_sw_init(struct amdgpu_ip_block *ip_block) 
			}

		}

	}

	/* TODO: Add queue reset mask when FW fully supports it */

	adev->gfx.gfx_supported_reset =

		amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]);

	adev->gfx.compute_supported_reset =

		amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]);



	r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE, 0);

	if (r) {