Commit 6cab3e26 authored by Simona Vetter's avatar Simona Vetter
Browse files

Merge tag 'drm-etnaviv-next-2024-06-28' of https://git.pengutronix.de/git/lst/linux into drm-next 



- fix i.MX8MP NPU clock gating
- workaround FE register cdc issues on some cores
- fix DMA sync handling for cached buffers
- fix job timeout handling
- keep TS enabled on MMUv2 cores for improved performance

Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
From: Lucas Stach <l.stach@pengutronix.de>
Link: https://patchwork.freedesktop.org/patch/msgid/e8b91e2f18e6eaa722569dd21f559009064b1730.camel@pengutronix.de
parents 3ccf1b83 704d3d60

drivers/gpu/drm/etnaviv/cmdstream.xml.h

+48 −4
Original line number Diff line number Diff line
@@ -8,11 +8,11 @@ This file was generated by the rules-ng-ng headergen tool in this git repository 
git clone git://0x04.net/rules-ng-ng



The rules-ng-ng source files this header was generated from are:

- cmdstream.xml (  14094 bytes, from 2016-11-11 06:55:14)

- copyright.xml (   1597 bytes, from 2016-10-29 07:29:22)

- common.xml    (  23344 bytes, from 2016-11-10 15:14:07)

- cmdstream.xml (  16933 bytes, from 2023-12-11 15:50:17)

- copyright.xml (   1597 bytes, from 2016-11-10 13:58:32)

- common.xml    (  35664 bytes, from 2023-12-06 10:55:32)



Copyright (C) 2012-2016 by the following authors:

Copyright (C) 2012-2023 by the following authors:

- Wladimir J. van der Laan <laanwj@gmail.com>

- Christian Gmeiner <christian.gmeiner@gmail.com>

- Lucas Stach <l.stach@pengutronix.de>
@@ -52,6 +52,9 @@ DEALINGS IN THE SOFTWARE. 
#define FE_OPCODE_RETURN					0x0000000b

#define FE_OPCODE_DRAW_INSTANCED				0x0000000c

#define FE_OPCODE_CHIP_SELECT					0x0000000d

#define FE_OPCODE_WAIT_FENCE					0x0000000f

#define FE_OPCODE_DRAW_INDIRECT					0x00000010

#define FE_OPCODE_SNAP_PAGES					0x00000013

#define PRIMITIVE_TYPE_POINTS					0x00000001

#define PRIMITIVE_TYPE_LINES					0x00000002

#define PRIMITIVE_TYPE_LINE_STRIP				0x00000003
@@ -192,6 +195,9 @@ DEALINGS IN THE SOFTWARE. 
#define VIV_FE_STALL_TOKEN_TO__MASK				0x00001f00

#define VIV_FE_STALL_TOKEN_TO__SHIFT				8

#define VIV_FE_STALL_TOKEN_TO(x)				(((x) << VIV_FE_STALL_TOKEN_TO__SHIFT) & VIV_FE_STALL_TOKEN_TO__MASK)

#define VIV_FE_STALL_TOKEN_UNK28__MASK				0x30000000

#define VIV_FE_STALL_TOKEN_UNK28__SHIFT				28

#define VIV_FE_STALL_TOKEN_UNK28(x)				(((x) << VIV_FE_STALL_TOKEN_UNK28__SHIFT) & VIV_FE_STALL_TOKEN_UNK28__MASK)



#define VIV_FE_CALL						0x00000000
@@ -266,5 +272,43 @@ DEALINGS IN THE SOFTWARE. 
#define VIV_FE_DRAW_INSTANCED_START_INDEX__SHIFT		0

#define VIV_FE_DRAW_INSTANCED_START_INDEX(x)			(((x) << VIV_FE_DRAW_INSTANCED_START_INDEX__SHIFT) & VIV_FE_DRAW_INSTANCED_START_INDEX__MASK)



#define VIV_FE_WAIT_FENCE					0x00000000



#define VIV_FE_WAIT_FENCE_HEADER				0x00000000

#define VIV_FE_WAIT_FENCE_HEADER_OP__MASK			0xf8000000

#define VIV_FE_WAIT_FENCE_HEADER_OP__SHIFT			27

#define VIV_FE_WAIT_FENCE_HEADER_OP_WAIT_FENCE			0x78000000

#define VIV_FE_WAIT_FENCE_HEADER_UNK16__MASK			0x00030000

#define VIV_FE_WAIT_FENCE_HEADER_UNK16__SHIFT			16

#define VIV_FE_WAIT_FENCE_HEADER_UNK16(x)			(((x) << VIV_FE_WAIT_FENCE_HEADER_UNK16__SHIFT) & VIV_FE_WAIT_FENCE_HEADER_UNK16__MASK)

#define VIV_FE_WAIT_FENCE_HEADER_WAITCOUNT__MASK		0x0000ffff

#define VIV_FE_WAIT_FENCE_HEADER_WAITCOUNT__SHIFT		0

#define VIV_FE_WAIT_FENCE_HEADER_WAITCOUNT(x)			(((x) << VIV_FE_WAIT_FENCE_HEADER_WAITCOUNT__SHIFT) & VIV_FE_WAIT_FENCE_HEADER_WAITCOUNT__MASK)



#define VIV_FE_WAIT_FENCE_ADDRESS				0x00000004



#define VIV_FE_DRAW_INDIRECT					0x00000000



#define VIV_FE_DRAW_INDIRECT_HEADER				0x00000000

#define VIV_FE_DRAW_INDIRECT_HEADER_OP__MASK			0xf8000000

#define VIV_FE_DRAW_INDIRECT_HEADER_OP__SHIFT			27

#define VIV_FE_DRAW_INDIRECT_HEADER_OP_DRAW_INDIRECT		0x80000000

#define VIV_FE_DRAW_INDIRECT_HEADER_INDEXED			0x00000100

#define VIV_FE_DRAW_INDIRECT_HEADER_TYPE__MASK			0x0000000f

#define VIV_FE_DRAW_INDIRECT_HEADER_TYPE__SHIFT			0

#define VIV_FE_DRAW_INDIRECT_HEADER_TYPE(x)			(((x) << VIV_FE_DRAW_INDIRECT_HEADER_TYPE__SHIFT) & VIV_FE_DRAW_INDIRECT_HEADER_TYPE__MASK)



#define VIV_FE_DRAW_INDIRECT_ADDRESS				0x00000004



#define VIV_FE_SNAP_PAGES					0x00000000



#define VIV_FE_SNAP_PAGES_HEADER				0x00000000

#define VIV_FE_SNAP_PAGES_HEADER_OP__MASK			0xf8000000

#define VIV_FE_SNAP_PAGES_HEADER_OP__SHIFT			27

#define VIV_FE_SNAP_PAGES_HEADER_OP_SNAP_PAGES			0x98000000

#define VIV_FE_SNAP_PAGES_HEADER_UNK0__MASK			0x0000001f

#define VIV_FE_SNAP_PAGES_HEADER_UNK0__SHIFT			0

#define VIV_FE_SNAP_PAGES_HEADER_UNK0(x)			(((x) << VIV_FE_SNAP_PAGES_HEADER_UNK0__SHIFT) & VIV_FE_SNAP_PAGES_HEADER_UNK0__MASK)





#endif /* CMDSTREAM_XML */

drivers/gpu/drm/etnaviv/common.xml.h

+7 −5
Original line number Diff line number Diff line
@@ -8,12 +8,12 @@ This file was generated by the rules-ng-ng headergen tool in this git repository 
git clone git://0x04.net/rules-ng-ng



The rules-ng-ng source files this header was generated from are:

- texdesc_3d.xml (   3183 bytes, from 2017-12-18 16:51:59)

- copyright.xml  (   1597 bytes, from 2016-12-08 16:37:56)

- common.xml     (  35468 bytes, from 2018-01-22 13:48:54)

- common_3d.xml  (  14615 bytes, from 2017-12-18 16:51:59)

- texdesc_3d.xml (   3183 bytes, from 2022-11-18 09:38:25)

- copyright.xml  (   1597 bytes, from 2016-11-10 13:58:32)

- common.xml     (  35664 bytes, from 2023-12-06 10:55:32)

- common_3d.xml  (  15069 bytes, from 2023-11-22 10:05:24)



Copyright (C) 2012-2018 by the following authors:

Copyright (C) 2012-2023 by the following authors:

- Wladimir J. van der Laan <laanwj@gmail.com>

- Christian Gmeiner <christian.gmeiner@gmail.com>

- Lucas Stach <l.stach@pengutronix.de>
@@ -65,6 +65,7 @@ DEALINGS IN THE SOFTWARE. 
#define chipModel_GC520						0x00000520

#define chipModel_GC530						0x00000530

#define chipModel_GC600						0x00000600

#define chipModel_GC620						0x00000620

#define chipModel_GC700						0x00000700

#define chipModel_GC800						0x00000800

#define chipModel_GC860						0x00000860
@@ -481,5 +482,6 @@ DEALINGS IN THE SOFTWARE. 
#define chipMinorFeatures11_NN_INTERLEVE8			0x00000008

#define chipMinorFeatures11_TP_REORDER				0x00000010

#define chipMinorFeatures11_PE_DEPTH_ONLY_OQFIX			0x00000020

#define chipMinorFeatures12_G2D_DEC400EX			0x00000020



#endif /* COMMON_XML */

drivers/gpu/drm/etnaviv/etnaviv_dump.c

+2 −3
Original line number Diff line number Diff line
@@ -159,8 +159,7 @@ void etnaviv_core_dump(struct etnaviv_gem_submit *submit) 
	file_size += sizeof(*iter.hdr) * n_obj;



	/* Allocate the file in vmalloc memory, it's likely to be big */

	iter.start = __vmalloc(file_size, GFP_KERNEL | __GFP_NOWARN |

			__GFP_NORETRY);

	iter.start = __vmalloc(file_size, GFP_NOWAIT);

	if (!iter.start) {

		mutex_unlock(&submit->mmu_context->lock);

		dev_warn(gpu->dev, "failed to allocate devcoredump file\n");
@@ -230,5 +229,5 @@ void etnaviv_core_dump(struct etnaviv_gem_submit *submit) 


	etnaviv_core_dump_header(&iter, ETDUMP_BUF_END, iter.data);



	dev_coredumpv(gpu->dev, iter.start, iter.data - iter.start, GFP_KERNEL);

	dev_coredumpv(gpu->dev, iter.start, iter.data - iter.start, GFP_NOWAIT);

}

drivers/gpu/drm/etnaviv/etnaviv_gem.c

+4 −2
Original line number Diff line number Diff line
@@ -355,9 +355,11 @@ static void *etnaviv_gem_vmap_impl(struct etnaviv_gem_object *obj) 


static inline enum dma_data_direction etnaviv_op_to_dma_dir(u32 op)

{

	if (op & ETNA_PREP_READ)

	op &= ETNA_PREP_READ | ETNA_PREP_WRITE;



	if (op == ETNA_PREP_READ)

		return DMA_FROM_DEVICE;

	else if (op & ETNA_PREP_WRITE)

	else if (op == ETNA_PREP_WRITE)

		return DMA_TO_DEVICE;

	else

		return DMA_BIDIRECTIONAL;

drivers/gpu/drm/etnaviv/etnaviv_gpu.c

+47 −36
Original line number Diff line number Diff line
@@ -172,10 +172,12 @@ int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value) 
	return 0;

}



static inline bool etnaviv_is_model_rev(struct etnaviv_gpu *gpu, u32 model, u32 revision)

{

	return gpu->identity.model == model &&

	       gpu->identity.revision == revision;

}



#define etnaviv_is_model_rev(gpu, mod, rev) \

	((gpu)->identity.model == chipModel_##mod && \

	 (gpu)->identity.revision == rev)

#define etnaviv_field(val, field) \

	(((val) & field##__MASK) >> field##__SHIFT)
@@ -281,7 +283,7 @@ static void etnaviv_hw_specs(struct etnaviv_gpu *gpu) 


	switch (gpu->identity.instruction_count) {

	case 0:

		if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||

		if (etnaviv_is_model_rev(gpu, 0x2000, 0x5108) ||

		    gpu->identity.model == chipModel_GC880)

			gpu->identity.instruction_count = 512;

		else
@@ -315,17 +317,17 @@ static void etnaviv_hw_specs(struct etnaviv_gpu *gpu) 
	 * For some cores, two varyings are consumed for position, so the

	 * maximum varying count needs to be reduced by one.

	 */

	if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) ||

	    etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||

	    etnaviv_is_model_rev(gpu, GC4000, 0x5245) ||

	    etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||

	    etnaviv_is_model_rev(gpu, GC3000, 0x5435) ||

	    etnaviv_is_model_rev(gpu, GC2200, 0x5244) ||

	    etnaviv_is_model_rev(gpu, GC2100, 0x5108) ||

	    etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||

	    etnaviv_is_model_rev(gpu, GC1500, 0x5246) ||

	    etnaviv_is_model_rev(gpu, GC880, 0x5107) ||

	    etnaviv_is_model_rev(gpu, GC880, 0x5106))

	if (etnaviv_is_model_rev(gpu, 0x5000, 0x5434) ||

	    etnaviv_is_model_rev(gpu, 0x4000, 0x5222) ||

	    etnaviv_is_model_rev(gpu, 0x4000, 0x5245) ||

	    etnaviv_is_model_rev(gpu, 0x4000, 0x5208) ||

	    etnaviv_is_model_rev(gpu, 0x3000, 0x5435) ||

	    etnaviv_is_model_rev(gpu, 0x2200, 0x5244) ||

	    etnaviv_is_model_rev(gpu, 0x2100, 0x5108) ||

	    etnaviv_is_model_rev(gpu, 0x2000, 0x5108) ||

	    etnaviv_is_model_rev(gpu, 0x1500, 0x5246) ||

	    etnaviv_is_model_rev(gpu, 0x880, 0x5107) ||

	    etnaviv_is_model_rev(gpu, 0x880, 0x5106))

		gpu->identity.varyings_count -= 1;

}
@@ -351,7 +353,7 @@ static void etnaviv_hw_identify(struct etnaviv_gpu *gpu) 
		 * Reading these two registers on GC600 rev 0x19 result in a

		 * unhandled fault: external abort on non-linefetch

		 */

		if (!etnaviv_is_model_rev(gpu, GC600, 0x19)) {

		if (!etnaviv_is_model_rev(gpu, 0x600, 0x19)) {

			gpu->identity.product_id = gpu_read(gpu, VIVS_HI_CHIP_PRODUCT_ID);

			gpu->identity.eco_id = gpu_read(gpu, VIVS_HI_CHIP_ECO_ID);

		}
@@ -368,7 +370,7 @@ static void etnaviv_hw_identify(struct etnaviv_gpu *gpu) 
		}



		/* Another special case */

		if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) {

		if (etnaviv_is_model_rev(gpu, 0x300, 0x2201)) {

			u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME);



			if (chipDate == 0x20080814 && chipTime == 0x12051100) {
@@ -387,15 +389,15 @@ static void etnaviv_hw_identify(struct etnaviv_gpu *gpu) 
		 * Fix model/rev here, so all other places can refer to this

		 * core by its real identity.

		 */

		if (etnaviv_is_model_rev(gpu, GC2000, 0xffff5450)) {

		if (etnaviv_is_model_rev(gpu, 0x2000, 0xffff5450)) {

			gpu->identity.model = chipModel_GC3000;

			gpu->identity.revision &= 0xffff;

		}



		if (etnaviv_is_model_rev(gpu, GC1000, 0x5037) && (chipDate == 0x20120617))

		if (etnaviv_is_model_rev(gpu, 0x1000, 0x5037) && (chipDate == 0x20120617))

			gpu->identity.eco_id = 1;



		if (etnaviv_is_model_rev(gpu, GC320, 0x5303) && (chipDate == 0x20140511))

		if (etnaviv_is_model_rev(gpu, 0x320, 0x5303) && (chipDate == 0x20140511))

			gpu->identity.eco_id = 1;

	}
@@ -641,17 +643,23 @@ static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu) 
		pmc |= BIT(15); /* Unknown bit */



	/* Disable TX clock gating on affected core revisions. */

	if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||

	    etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||

	    etnaviv_is_model_rev(gpu, GC7000, 0x6202) ||

	    etnaviv_is_model_rev(gpu, GC7000, 0x6203))

	if (etnaviv_is_model_rev(gpu, 0x4000, 0x5222) ||

	    etnaviv_is_model_rev(gpu, 0x2000, 0x5108) ||

	    etnaviv_is_model_rev(gpu, 0x7000, 0x6202) ||

	    etnaviv_is_model_rev(gpu, 0x7000, 0x6203))

		pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX;



	/* Disable SE and RA clock gating on affected core revisions. */

	if (etnaviv_is_model_rev(gpu, GC7000, 0x6202))

	if (etnaviv_is_model_rev(gpu, 0x7000, 0x6202))

		pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE |

		       VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA;



	/* Disable SH_EU clock gating on affected core revisions. */

	if (etnaviv_is_model_rev(gpu, 0x8000, 0x7200) ||

	    etnaviv_is_model_rev(gpu, 0x8000, 0x8002) ||

	    etnaviv_is_model_rev(gpu, 0x9200, 0x6304))

		pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SH_EU;



	pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ;

	pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ;
@@ -701,14 +709,14 @@ static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu) 
	 */

	u32 pulse_eater = 0x01590880;



	if (etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||

	    etnaviv_is_model_rev(gpu, GC4000, 0x5222)) {

	if (etnaviv_is_model_rev(gpu, 0x4000, 0x5208) ||

	    etnaviv_is_model_rev(gpu, 0x4000, 0x5222)) {

		pulse_eater |= BIT(23);



	}



	if (etnaviv_is_model_rev(gpu, GC1000, 0x5039) ||

	    etnaviv_is_model_rev(gpu, GC1000, 0x5040)) {

	if (etnaviv_is_model_rev(gpu, 0x1000, 0x5039) ||

	    etnaviv_is_model_rev(gpu, 0x1000, 0x5040)) {

		pulse_eater &= ~BIT(16);

		pulse_eater |= BIT(17);

	}
@@ -729,8 +737,8 @@ static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu) 
	WARN_ON(!(gpu->state == ETNA_GPU_STATE_IDENTIFIED ||

		  gpu->state == ETNA_GPU_STATE_RESET));



	if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) ||

	     etnaviv_is_model_rev(gpu, GC320, 0x5220)) &&

	if ((etnaviv_is_model_rev(gpu, 0x320, 0x5007) ||

	     etnaviv_is_model_rev(gpu, 0x320, 0x5220)) &&

	    gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) {

		u32 mc_memory_debug;
@@ -756,7 +764,7 @@ static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu) 
		  VIVS_HI_AXI_CONFIG_ARCACHE(2));



	/* GC2000 rev 5108 needs a special bus config */

	if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) {

	if (etnaviv_is_model_rev(gpu, 0x2000, 0x5108)) {

		u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG);

		bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK |

				VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK);
@@ -855,12 +863,15 @@ int etnaviv_gpu_init(struct etnaviv_gpu *gpu) 
	 *

	 * On MC1.0 cores the linear window offset is ignored by the TS engine,

	 * leading to inconsistent memory views. Avoid using the offset on those

	 * cores if possible, otherwise disable the TS feature.

	 * cores if possible, otherwise disable the TS feature. MMUv2 doesn't

	 * expose this issue, as all TS accesses are MMU translated, so the

	 * linear window offset won't be used.

	 */

	cmdbuf_paddr = ALIGN_DOWN(etnaviv_cmdbuf_get_pa(&gpu->buffer), SZ_128M);



	if (!(gpu->identity.features & chipFeatures_PIPE_3D) ||

	    (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) {

	    (gpu->identity.minor_features0 & chipMinorFeatures0_MC20) ||

	    (gpu->identity.minor_features1 & chipMinorFeatures1_MMU_VERSION)) {

		if (cmdbuf_paddr >= SZ_2G)

			priv->mmu_global->memory_base = SZ_2G;

		else
@@ -1537,6 +1548,7 @@ static irqreturn_t irq_handler(int irq, void *data) 
	u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE);



	if (intr != 0) {

		ktime_t now = ktime_get();

		int event;



		pm_runtime_mark_last_busy(gpu->dev);
@@ -1586,7 +1598,7 @@ static irqreturn_t irq_handler(int irq, void *data) 
			 */

			if (fence_after(fence->seqno, gpu->completed_fence))

				gpu->completed_fence = fence->seqno;

			dma_fence_signal(fence);

			dma_fence_signal_timestamp(fence, now);



			event_free(gpu, event);

		}
@@ -1975,7 +1987,6 @@ static const struct dev_pm_ops etnaviv_gpu_pm_ops = { 
struct platform_driver etnaviv_gpu_driver = {

	.driver = {

		.name = "etnaviv-gpu",

		.owner = THIS_MODULE,

		.pm = pm_ptr(&etnaviv_gpu_pm_ops),

		.of_match_table = etnaviv_gpu_match,

	},