Commit 6d0ebb39 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2024-08-29' of... 

Merge tag 'drm-intel-next-2024-08-29' of https://gitlab.freedesktop.org/drm/i915/kernel

 into drm-next

Cross-driver (xe-core) Changes:
- Require BMG scanout buffers to be 64k physically aligned (Maarten)

Core (drm) Changes:
- Introducing Xe2 ccs modifiers for integrated and discrete graphics (Juha-Pekka)

Driver Changes:
- General cleanup and more work moving towards intel_display isolation (Jani)
- New display workaround (Suraj)
- Use correct cp_irq_count on HDCP (Suraj)
- eDP PSR fix when CRC is enabled (Jouni)
- Fix DP MST state after a sink reset (Imre)
- Fix Arrow Lake GSC firmware version (John)
- Use chained DSBs for LUT programming (Ville)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ZtCC0lJ0Zf3MoSdW@intel.com
parents 8bdb468d b5d4657e

drivers/gpu/drm/i915/display/intel_alpm.c

+27 −27
Original line number Diff line number Diff line
@@ -139,7 +139,7 @@ static int 
_lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp,

				  const struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *i915 = dp_to_i915(intel_dp);

	struct intel_display *display = to_intel_display(intel_dp);

	int aux_less_wake_time, aux_less_wake_lines, silence_period,

		lfps_half_cycle;
@@ -158,7 +158,7 @@ _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp, 
	    lfps_half_cycle > PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK)

		return false;



	if (i915->display.params.psr_safest_params)

	if (display->params.psr_safest_params)

		aux_less_wake_lines = ALPM_CTL_AUX_LESS_WAKE_TIME_MASK;



	intel_dp->alpm_parameters.aux_less_wake_lines = aux_less_wake_lines;
@@ -171,10 +171,10 @@ _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp, 
static bool _lnl_compute_alpm_params(struct intel_dp *intel_dp,

				     const struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *i915 = dp_to_i915(intel_dp);

	struct intel_display *display = to_intel_display(intel_dp);

	int check_entry_lines;



	if (DISPLAY_VER(i915) < 20)

	if (DISPLAY_VER(display) < 20)

		return true;



	/* ALPM Entry Check = 2 + CEILING( 5us /tline ) */
@@ -187,7 +187,7 @@ static bool _lnl_compute_alpm_params(struct intel_dp *intel_dp, 
	if (!_lnl_compute_aux_less_alpm_params(intel_dp, crtc_state))

		return false;



	if (i915->display.params.psr_safest_params)

	if (display->params.psr_safest_params)

		check_entry_lines = 15;



	intel_dp->alpm_parameters.check_entry_lines = check_entry_lines;
@@ -212,9 +212,9 @@ static int tgl_io_buffer_wake_time(void) 


static int io_buffer_wake_time(const struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);

	struct intel_display *display = to_intel_display(crtc_state);



	if (DISPLAY_VER(i915) >= 12)

	if (DISPLAY_VER(display) >= 12)

		return tgl_io_buffer_wake_time();

	else

		return skl_io_buffer_wake_time();
@@ -223,7 +223,7 @@ static int io_buffer_wake_time(const struct intel_crtc_state *crtc_state) 
bool intel_alpm_compute_params(struct intel_dp *intel_dp,

			       const struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *i915 = dp_to_i915(intel_dp);

	struct intel_display *display = to_intel_display(intel_dp);

	int io_wake_lines, io_wake_time, fast_wake_lines, fast_wake_time;

	int tfw_exit_latency = 20; /* eDP spec */

	int phy_wake = 4;	   /* eDP spec */
@@ -236,9 +236,9 @@ bool intel_alpm_compute_params(struct intel_dp *intel_dp, 
	fast_wake_time = precharge + preamble + phy_wake +

		tfw_exit_latency;



	if (DISPLAY_VER(i915) >= 20)

	if (DISPLAY_VER(display) >= 20)

		max_wake_lines = 68;

	else if (DISPLAY_VER(i915) >= 12)

	else if (DISPLAY_VER(display) >= 12)

		max_wake_lines = 12;

	else

		max_wake_lines = 8;
@@ -255,7 +255,7 @@ bool intel_alpm_compute_params(struct intel_dp *intel_dp, 
	if (!_lnl_compute_alpm_params(intel_dp, crtc_state))

		return false;



	if (i915->display.params.psr_safest_params)

	if (display->params.psr_safest_params)

		io_wake_lines = fast_wake_lines = max_wake_lines;



	/* According to Bspec lower limit should be set as 7 lines. */
@@ -269,7 +269,7 @@ void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp, 
				    struct intel_crtc_state *crtc_state,

				    struct drm_connector_state *conn_state)

{

	struct drm_i915_private *i915 = dp_to_i915(intel_dp);

	struct intel_display *display = to_intel_display(intel_dp);

	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;

	int waketime_in_lines, first_sdp_position;

	int context_latency, guardband;
@@ -277,7 +277,7 @@ void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp, 
	if (!intel_dp_is_edp(intel_dp))

		return;



	if (DISPLAY_VER(i915) < 20)

	if (DISPLAY_VER(display) < 20)

		return;



	if (!intel_dp->as_sdp_supported)
@@ -309,13 +309,13 @@ void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp, 
static void lnl_alpm_configure(struct intel_dp *intel_dp,

			       const struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);

	struct intel_display *display = to_intel_display(intel_dp);

	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

	enum port port = dp_to_dig_port(intel_dp)->base.port;

	u32 alpm_ctl;



	if (DISPLAY_VER(dev_priv) < 20 || (!intel_dp->psr.sel_update_enabled &&

					   !intel_dp_is_edp(intel_dp)))

	if (DISPLAY_VER(display) < 20 ||

	    (!intel_dp->psr.sel_update_enabled && !intel_dp_is_edp(intel_dp)))

		return;



	/*
@@ -329,16 +329,16 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp, 
			ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS |

			ALPM_CTL_AUX_LESS_WAKE_TIME(intel_dp->alpm_parameters.aux_less_wake_lines);



		intel_de_write(dev_priv,

			       PORT_ALPM_CTL(dev_priv, port),

		intel_de_write(display,

			       PORT_ALPM_CTL(display, port),

			       PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE |

			       PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) |

			       PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) |

			       PORT_ALPM_CTL_SILENCE_PERIOD(

				       intel_dp->alpm_parameters.silence_period_sym_clocks));



		intel_de_write(dev_priv,

			       PORT_ALPM_LFPS_CTL(dev_priv, port),

		intel_de_write(display,

			       PORT_ALPM_LFPS_CTL(display, port),

			       PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(10) |

			       PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(

				       intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms) |
@@ -356,7 +356,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp, 


	alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(intel_dp->alpm_parameters.check_entry_lines);



	intel_de_write(dev_priv, ALPM_CTL(dev_priv, cpu_transcoder), alpm_ctl);

	intel_de_write(display, ALPM_CTL(display, cpu_transcoder), alpm_ctl);

}



void intel_alpm_configure(struct intel_dp *intel_dp,
@@ -368,14 +368,14 @@ void intel_alpm_configure(struct intel_dp *intel_dp, 
static int i915_edp_lobf_info_show(struct seq_file *m, void *data)

{

	struct intel_connector *connector = m->private;

	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);

	struct intel_display *display = to_intel_display(connector);

	struct drm_crtc *crtc;

	struct intel_crtc_state *crtc_state;

	enum transcoder cpu_transcoder;

	u32 alpm_ctl;

	int ret;



	ret = drm_modeset_lock_single_interruptible(&dev_priv->drm.mode_config.connection_mutex);

	ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);

	if (ret)

		return ret;
@@ -387,14 +387,14 @@ static int i915_edp_lobf_info_show(struct seq_file *m, void *data) 


	crtc_state = to_intel_crtc_state(crtc->state);

	cpu_transcoder = crtc_state->cpu_transcoder;

	alpm_ctl = intel_de_read(dev_priv, ALPM_CTL(dev_priv, cpu_transcoder));

	alpm_ctl = intel_de_read(display, ALPM_CTL(display, cpu_transcoder));

	seq_printf(m, "LOBF status: %s\n", str_enabled_disabled(alpm_ctl & ALPM_CTL_LOBF_ENABLE));

	seq_printf(m, "Aux-wake alpm status: %s\n",

		   str_enabled_disabled(!(alpm_ctl & ALPM_CTL_ALPM_AUX_LESS_ENABLE)));

	seq_printf(m, "Aux-less alpm status: %s\n",

		   str_enabled_disabled(alpm_ctl & ALPM_CTL_ALPM_AUX_LESS_ENABLE));

out:

	drm_modeset_unlock(&dev_priv->drm.mode_config.connection_mutex);

	drm_modeset_unlock(&display->drm->mode_config.connection_mutex);



	return ret;

}
@@ -403,10 +403,10 @@ DEFINE_SHOW_ATTRIBUTE(i915_edp_lobf_info); 


void intel_alpm_lobf_debugfs_add(struct intel_connector *connector)

{

	struct drm_i915_private *i915 = to_i915(connector->base.dev);

	struct intel_display *display = to_intel_display(connector);

	struct dentry *root = connector->base.debugfs_entry;



	if (DISPLAY_VER(i915) < 20 ||

	if (DISPLAY_VER(display) < 20 ||

	    connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)

		return;

drivers/gpu/drm/i915/display/intel_atomic.c

+4 −2
Original line number Diff line number Diff line
@@ -276,7 +276,8 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc) 
	crtc_state->do_async_flip = false;

	crtc_state->fb_bits = 0;

	crtc_state->update_planes = 0;

	crtc_state->dsb = NULL;

	crtc_state->dsb_color_vblank = NULL;

	crtc_state->dsb_color_commit = NULL;



	return &crtc_state->uapi;

}
@@ -310,7 +311,8 @@ intel_crtc_destroy_state(struct drm_crtc *crtc, 
{

	struct intel_crtc_state *crtc_state = to_intel_crtc_state(state);



	drm_WARN_ON(crtc->dev, crtc_state->dsb);

	drm_WARN_ON(crtc->dev, crtc_state->dsb_color_vblank);

	drm_WARN_ON(crtc->dev, crtc_state->dsb_color_commit);



	__drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);

	intel_crtc_free_hw_state(crtc_state);

drivers/gpu/drm/i915/display/intel_backlight.c

+5 −5
Original line number Diff line number Diff line
@@ -1011,7 +1011,7 @@ static u32 cnp_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) 
{

	struct drm_i915_private *i915 = to_i915(connector->base.dev);



	return DIV_ROUND_CLOSEST(KHz(RUNTIME_INFO(i915)->rawclk_freq),

	return DIV_ROUND_CLOSEST(KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq),

				 pwm_freq_hz);

}
@@ -1073,7 +1073,7 @@ static u32 pch_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) 
{

	struct drm_i915_private *i915 = to_i915(connector->base.dev);



	return DIV_ROUND_CLOSEST(KHz(RUNTIME_INFO(i915)->rawclk_freq),

	return DIV_ROUND_CLOSEST(KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq),

				 pwm_freq_hz * 128);

}
@@ -1091,7 +1091,7 @@ static u32 i9xx_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) 
	int clock;



	if (IS_PINEVIEW(i915))

		clock = KHz(RUNTIME_INFO(i915)->rawclk_freq);

		clock = KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq);

	else

		clock = KHz(i915->display.cdclk.hw.cdclk);
@@ -1109,7 +1109,7 @@ static u32 i965_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) 
	int clock;



	if (IS_G4X(i915))

		clock = KHz(RUNTIME_INFO(i915)->rawclk_freq);

		clock = KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq);

	else

		clock = KHz(i915->display.cdclk.hw.cdclk);
@@ -1133,7 +1133,7 @@ static u32 vlv_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) 
			clock = MHz(25);

		mul = 16;

	} else {

		clock = KHz(RUNTIME_INFO(i915)->rawclk_freq);

		clock = KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq);

		mul = 128;

	}

drivers/gpu/drm/i915/display/intel_color.c

+37 −19
Original line number Diff line number Diff line
@@ -1313,8 +1313,8 @@ static void ilk_lut_write(const struct intel_crtc_state *crtc_state, 
{

	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);



	if (crtc_state->dsb)

		intel_dsb_reg_write(crtc_state->dsb, reg, val);

	if (crtc_state->dsb_color_vblank)

		intel_dsb_reg_write(crtc_state->dsb_color_vblank, reg, val);

	else

		intel_de_write_fw(i915, reg, val);

}
@@ -1337,15 +1337,15 @@ static void ilk_load_lut_8(const struct intel_crtc_state *crtc_state, 
	 * unless we either write each entry twice,

	 * or use non-posted writes

	 */

	if (crtc_state->dsb)

		intel_dsb_nonpost_start(crtc_state->dsb);

	if (crtc_state->dsb_color_vblank)

		intel_dsb_nonpost_start(crtc_state->dsb_color_vblank);



	for (i = 0; i < 256; i++)

		ilk_lut_write(crtc_state, LGC_PALETTE(pipe, i),

			      i9xx_lut_8(&lut[i]));



	if (crtc_state->dsb)

		intel_dsb_nonpost_end(crtc_state->dsb);

	if (crtc_state->dsb_color_vblank)

		intel_dsb_nonpost_end(crtc_state->dsb_color_vblank);

}



static void ilk_load_lut_10(const struct intel_crtc_state *crtc_state,
@@ -1870,7 +1870,7 @@ void intel_color_load_luts(const struct intel_crtc_state *crtc_state) 
{

	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);



	if (crtc_state->dsb)

	if (crtc_state->dsb_color_vblank)

		return;



	i915->display.funcs.color->load_luts(crtc_state);
@@ -1890,8 +1890,8 @@ void intel_color_commit_arm(const struct intel_crtc_state *crtc_state) 


	i915->display.funcs.color->color_commit_arm(crtc_state);



	if (crtc_state->dsb)

		intel_dsb_commit(crtc_state->dsb, true);

	if (crtc_state->dsb_color_commit)

		intel_dsb_commit(crtc_state->dsb_color_commit, false);

}



void intel_color_post_update(const struct intel_crtc_state *crtc_state)
@@ -1919,33 +1919,51 @@ void intel_color_prepare_commit(struct intel_atomic_state *state, 
	if (!crtc_state->pre_csc_lut && !crtc_state->post_csc_lut)

		return;



	crtc_state->dsb = intel_dsb_prepare(state, crtc, INTEL_DSB_0, 1024);

	if (!crtc_state->dsb)

	crtc_state->dsb_color_vblank = intel_dsb_prepare(state, crtc, INTEL_DSB_1, 1024);

	if (!crtc_state->dsb_color_vblank)

		return;



	i915->display.funcs.color->load_luts(crtc_state);



	intel_dsb_finish(crtc_state->dsb);

	intel_dsb_finish(crtc_state->dsb_color_vblank);



	crtc_state->dsb_color_commit = intel_dsb_prepare(state, crtc, INTEL_DSB_0, 16);

	if (!crtc_state->dsb_color_commit) {

		intel_dsb_cleanup(crtc_state->dsb_color_vblank);

		crtc_state->dsb_color_vblank = NULL;

		return;

	}



	intel_dsb_chain(state, crtc_state->dsb_color_commit,

			crtc_state->dsb_color_vblank, true);



	intel_dsb_finish(crtc_state->dsb_color_commit);

}



void intel_color_cleanup_commit(struct intel_crtc_state *crtc_state)

{

	if (!crtc_state->dsb)

		return;

	if (crtc_state->dsb_color_commit) {

		intel_dsb_cleanup(crtc_state->dsb_color_commit);

		crtc_state->dsb_color_commit = NULL;

	}



	intel_dsb_cleanup(crtc_state->dsb);

	crtc_state->dsb = NULL;

	if (crtc_state->dsb_color_vblank) {

		intel_dsb_cleanup(crtc_state->dsb_color_vblank);

		crtc_state->dsb_color_vblank = NULL;

	}

}



void intel_color_wait_commit(const struct intel_crtc_state *crtc_state)

{

	if (crtc_state->dsb)

		intel_dsb_wait(crtc_state->dsb);

	if (crtc_state->dsb_color_commit)

		intel_dsb_wait(crtc_state->dsb_color_commit);

	if (crtc_state->dsb_color_vblank)

		intel_dsb_wait(crtc_state->dsb_color_vblank);

}



bool intel_color_uses_dsb(const struct intel_crtc_state *crtc_state)

{

	return crtc_state->dsb;

	return crtc_state->dsb_color_vblank;

}



static bool intel_can_preload_luts(struct intel_atomic_state *state,

drivers/gpu/drm/i915/display/intel_ddi.c

+1 −1
Original line number Diff line number Diff line
@@ -4900,7 +4900,7 @@ void intel_ddi_init(struct intel_display *display, 
	 * driver.  In that case we should skip initializing the corresponding

	 * outputs.

	 */

	if (intel_hti_uses_phy(dev_priv, phy)) {

	if (intel_hti_uses_phy(display, phy)) {

		drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n",

			    port_name(port), phy_name(phy));

		return;