Commit 6d7d203c authored by Sam Protsenko's avatar Sam Protsenko Committed by Krzysztof Kozlowski
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clk: samsung: Pass register layout type explicitly to CLK_CPU() 



Use a dedicated enum field to explicitly specify which register layout
should be used for the CPU clock, instead of passing it as a bit flag.
This way it would be possible to keep the chip-specific data in some
array, where each chip structure could be accessed by its corresponding
layout index. It prepares clk-cpu.c for adding new chips support, which
might have different data for different CPU clusters.

No functional change.

Signed-off-by: default avatarSam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20240224202053.25313-9-semen.protsenko@linaro.org


Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
parent 338f1c25

drivers/clk/samsung/clk-cpu.c

+1 −1
Original line number Diff line number Diff line
@@ -465,7 +465,7 @@ static int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx, 
	cpuclk->lock = &ctx->lock;

	cpuclk->flags = clk_data->flags;

	cpuclk->clk_nb.notifier_call = exynos_cpuclk_notifier_cb;

	if (clk_data->flags & CLK_CPU_HAS_E5433_REGS_LAYOUT) {

	if (clk_data->reg_layout == CPUCLK_LAYOUT_E5433) {

		cpuclk->pre_rate_cb = exynos5433_cpuclk_pre_rate_change;

		cpuclk->post_rate_cb = exynos5433_cpuclk_post_rate_change;

	} else {

drivers/clk/samsung/clk-cpu.h

+10 −2
Original line number Diff line number Diff line
@@ -12,8 +12,16 @@ 
#define CLK_CPU_HAS_DIV1		BIT(0)

/* When ALT parent is active, debug clocks need safe divider values */

#define CLK_CPU_NEEDS_DEBUG_ALT_DIV	BIT(1)

/* The CPU clock registers have Exynos5433-compatible layout */

#define CLK_CPU_HAS_E5433_REGS_LAYOUT	BIT(2)



/**

 * enum exynos_cpuclk_layout - CPU clock registers layout compatibility

 * @CPUCLK_LAYOUT_E4210: Exynos4210 compatible layout

 * @CPUCLK_LAYOUT_E5433: Exynos5433 compatible layout

 */

enum exynos_cpuclk_layout {

	CPUCLK_LAYOUT_E4210,

	CPUCLK_LAYOUT_E5433,

};



/**

 * struct exynos_cpuclk_cfg_data - config data to setup cpu clocks

drivers/clk/samsung/clk-exynos3250.c

+1 −1
Original line number Diff line number Diff line
@@ -775,7 +775,7 @@ static const struct exynos_cpuclk_cfg_data e3250_armclk_d[] __initconst = { 


static const struct samsung_cpu_clock exynos3250_cpu_clks[] __initconst = {

	CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL_USER_C,

		CLK_CPU_HAS_DIV1, 0x14000, e3250_armclk_d),

		CLK_CPU_HAS_DIV1, 0x14000, CPUCLK_LAYOUT_E4210, e3250_armclk_d),

};



static void __init exynos3_core_down_clock(void __iomem *reg_base)

drivers/clk/samsung/clk-exynos4.c

+3 −3
Original line number Diff line number Diff line
@@ -1253,19 +1253,19 @@ static const struct exynos_cpuclk_cfg_data e4412_armclk_d[] __initconst = { 
static const struct samsung_cpu_clock exynos4210_cpu_clks[] __initconst = {

	CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_SCLK_MPLL,

		CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14000,

		e4210_armclk_d),

		CPUCLK_LAYOUT_E4210, e4210_armclk_d),

};



static const struct samsung_cpu_clock exynos4212_cpu_clks[] __initconst = {

	CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL_USER_C,

		CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14000,

		e4212_armclk_d),

		CPUCLK_LAYOUT_E4210, e4212_armclk_d),

};



static const struct samsung_cpu_clock exynos4412_cpu_clks[] __initconst = {

	CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL_USER_C,

		CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14000,

		e4412_armclk_d),

		CPUCLK_LAYOUT_E4210, e4412_armclk_d),

};



/* register exynos4 clocks */

drivers/clk/samsung/clk-exynos5250.c

+2 −1
Original line number Diff line number Diff line
@@ -777,7 +777,8 @@ static const struct exynos_cpuclk_cfg_data exynos5250_armclk_d[] __initconst = { 


static const struct samsung_cpu_clock exynos5250_cpu_clks[] __initconst = {

	CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL,

		CLK_CPU_HAS_DIV1, 0x0, exynos5250_armclk_d),

		CLK_CPU_HAS_DIV1, 0x0, CPUCLK_LAYOUT_E4210,

		exynos5250_armclk_d),

};



static const struct of_device_id ext_clk_match[] __initconst = {