Unverified Commit 6d8e604c authored by Palmer Dabbelt's avatar Palmer Dabbelt
Browse files

Merge patch series "Support Zve32[xf] and Zve64[xfd] Vector subextensions" 

Andy Chiu <andy.chiu@sifive.com> says:

The series composes of two parts. The first part Specifically,
patch 1 adds a comment at a callsite of riscv_setup_vsize to clarify how
vlenb is observed by the system. Patch 2 fixes the issue by failing the
boot process of a secondary core if vlenb mismatches.

Here is the organization of the series:
 - Patch 1, 2 provide a fix for mismatching vlen problem [1]. The
   solution is to fail secondary cores if their vlenb is not the same as
   the boot core.
 - Patch 3 is a cleanup for introducing ZVE* Vector subextensions. It
   gives the obsolete ISA parser the ability to expand ISA extensions for
   sigle letter extensions.
 - Patch 4, 5, 6 introduce Zve32x, Zve32f, Zve64x, Zve64f, Zve64d for isa
   parsing and hwprobe, and document about it.
 - Patch 7 makes has_vector() check against ZVE32X instead of V, so most
   userspace Vector supports will be available for bare ZVE32X.
 - Patch 8 updates the prctl test so that it runs on ZVE32X.

The series is tested on a QEMU and verified that booting, Vector
programs context-switch, signal, ptrace, prctl interfaces works when we
only report partial V from the ISA.

* b4-shazam-lts:
  selftest: run vector prctl test for ZVE32X
  riscv: vector: adjust minimum Vector requirement to ZVE32X
  riscv: hwprobe: add zve Vector subextensions into hwprobe interface
  riscv: cpufeature: add zve32[xf] and zve64[xfd] isa detection
  dt-bindings: riscv: add Zve32[xf] Zve64[xfd] ISA extension description
  riscv: cpufeature: call match_isa_ext() for single-letter extensions
  riscv: vector: add a comment when calling riscv_setup_vsize()
  riscv: smp: fail booting up smp if inconsistent vlen is detected

[Palmer: reorder the first two patches so I can merge the fix, and
rebase this on v6.10-rc1 so it's a little easier to manage.]

Link: https://lore.kernel.org/r/20240510-zve-detection-v5-0-0711bdd26c12@sifive.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parents 1613e604 edc96a2b

Documentation/arch/riscv/hwprobe.rst

+15 −0
Original line number Diff line number Diff line
@@ -192,6 +192,21 @@ The following keys are defined: 
       supported as defined in the RISC-V ISA manual starting from commit

       d8ab5c78c207 ("Zihintpause is ratified").



  * :c:macro:`RISCV_HWPROBE_EXT_ZVE32X`: The Vector sub-extension Zve32x is

    supported, as defined by version 1.0 of the RISC-V Vector extension manual.



  * :c:macro:`RISCV_HWPROBE_EXT_ZVE32F`: The Vector sub-extension Zve32f is

    supported, as defined by version 1.0 of the RISC-V Vector extension manual.



  * :c:macro:`RISCV_HWPROBE_EXT_ZVE64X`: The Vector sub-extension Zve64x is

    supported, as defined by version 1.0 of the RISC-V Vector extension manual.



  * :c:macro:`RISCV_HWPROBE_EXT_ZVE64F`: The Vector sub-extension Zve64f is

    supported, as defined by version 1.0 of the RISC-V Vector extension manual.



  * :c:macro:`RISCV_HWPROBE_EXT_ZVE64D`: The Vector sub-extension Zve64d is

    supported, as defined by version 1.0 of the RISC-V Vector extension manual.



* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance

  information about the selected set of processors.

Documentation/devicetree/bindings/riscv/extensions.yaml

+30 −0
Original line number Diff line number Diff line
@@ -381,6 +381,36 @@ properties: 
            instructions, as ratified in commit 56ed795 ("Update

            riscv-crypto-spec-vector.adoc") of riscv-crypto.



        - const: zve32f

          description:

            The standard Zve32f extension for embedded processors, as ratified

            in commit 6f702a2 ("Vector extensions are now ratified") of

            riscv-v-spec.



        - const: zve32x

          description:

            The standard Zve32x extension for embedded processors, as ratified

            in commit 6f702a2 ("Vector extensions are now ratified") of

            riscv-v-spec.



        - const: zve64d

          description:

            The standard Zve64d extension for embedded processors, as ratified

            in commit 6f702a2 ("Vector extensions are now ratified") of

            riscv-v-spec.



        - const: zve64f

          description:

            The standard Zve64f extension for embedded processors, as ratified

            in commit 6f702a2 ("Vector extensions are now ratified") of

            riscv-v-spec.



        - const: zve64x

          description:

            The standard Zve64x extension for embedded processors, as ratified

            in commit 6f702a2 ("Vector extensions are now ratified") of

            riscv-v-spec.



        - const: zvfh

          description:

            The standard Zvfh extension for vectored half-precision

arch/riscv/include/asm/hwcap.h

+5 −0
Original line number Diff line number Diff line
@@ -81,6 +81,11 @@ 
#define RISCV_ISA_EXT_ZTSO		72

#define RISCV_ISA_EXT_ZACAS		73

#define RISCV_ISA_EXT_XANDESPMU		74

#define RISCV_ISA_EXT_ZVE32X		75

#define RISCV_ISA_EXT_ZVE32F		76

#define RISCV_ISA_EXT_ZVE64X		77

#define RISCV_ISA_EXT_ZVE64F		78

#define RISCV_ISA_EXT_ZVE64D		79



#define RISCV_ISA_EXT_XLINUXENVCFG	127

arch/riscv/include/asm/vector.h

+5 −5
Original line number Diff line number Diff line
@@ -37,7 +37,7 @@ static inline u32 riscv_v_flags(void) 


static __always_inline bool has_vector(void)

{

	return riscv_has_extension_unlikely(RISCV_ISA_EXT_v);

	return riscv_has_extension_unlikely(RISCV_ISA_EXT_ZVE32X);

}



static inline void __riscv_v_vstate_clean(struct pt_regs *regs)
@@ -91,7 +91,7 @@ static __always_inline void __vstate_csr_restore(struct __riscv_v_ext_state *src 
{

	asm volatile (

		".option push\n\t"

		".option arch, +v\n\t"

		".option arch, +zve32x\n\t"

		"vsetvl	 x0, %2, %1\n\t"

		".option pop\n\t"

		"csrw	" __stringify(CSR_VSTART) ", %0\n\t"
@@ -109,7 +109,7 @@ static inline void __riscv_v_vstate_save(struct __riscv_v_ext_state *save_to, 
	__vstate_csr_save(save_to);

	asm volatile (

		".option push\n\t"

		".option arch, +v\n\t"

		".option arch, +zve32x\n\t"

		"vsetvli	%0, x0, e8, m8, ta, ma\n\t"

		"vse8.v		v0, (%1)\n\t"

		"add		%1, %1, %0\n\t"
@@ -131,7 +131,7 @@ static inline void __riscv_v_vstate_restore(struct __riscv_v_ext_state *restore_ 
	riscv_v_enable();

	asm volatile (

		".option push\n\t"

		".option arch, +v\n\t"

		".option arch, +zve32x\n\t"

		"vsetvli	%0, x0, e8, m8, ta, ma\n\t"

		"vle8.v		v0, (%1)\n\t"

		"add		%1, %1, %0\n\t"
@@ -153,7 +153,7 @@ static inline void __riscv_v_vstate_discard(void) 
	riscv_v_enable();

	asm volatile (

		".option push\n\t"

		".option arch, +v\n\t"

		".option arch, +zve32x\n\t"

		"vsetvli	%0, x0, e8, m8, ta, ma\n\t"

		"vmv.v.i	v0, -1\n\t"

		"vmv.v.i	v8, -1\n\t"

arch/riscv/include/uapi/asm/hwprobe.h

+5 −0
Original line number Diff line number Diff line
@@ -60,6 +60,11 @@ struct riscv_hwprobe { 
#define		RISCV_HWPROBE_EXT_ZACAS		(1ULL << 34)

#define		RISCV_HWPROBE_EXT_ZICOND	(1ULL << 35)

#define		RISCV_HWPROBE_EXT_ZIHINTPAUSE	(1ULL << 36)

#define		RISCV_HWPROBE_EXT_ZVE32X	(1ULL << 37)

#define		RISCV_HWPROBE_EXT_ZVE32F	(1ULL << 38)

#define		RISCV_HWPROBE_EXT_ZVE64X	(1ULL << 39)

#define		RISCV_HWPROBE_EXT_ZVE64F	(1ULL << 40)

#define		RISCV_HWPROBE_EXT_ZVE64D	(1ULL << 41)

#define RISCV_HWPROBE_KEY_CPUPERF_0	5

#define		RISCV_HWPROBE_MISALIGNED_UNKNOWN	(0 << 0)

#define		RISCV_HWPROBE_MISALIGNED_EMULATED	(1 << 0)