Commit 6e37877d authored by Russell King (Oracle)'s avatar Russell King (Oracle) Committed by Jakub Kicinski
Browse files

net: stmmac: use common LPI_CTRL_STATUS bit definitions 



The bit definitions for the LPI control/status register are
identical across all MAC versions, with the exception that some
bits may not be implemented. Provide definitions for bits in this
register in common.h, convert to use them, and remove the core-
specific definitions.

Signed-off-by: default avatarRussell King (Oracle) <rmk+kernel@armlinux.org.uk>
Link: https://patch.msgid.link/E1tffdn-003ZIN-9p@rmk-PC.armlinux.org.uk


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 9b6649a8

drivers/net/ethernet/stmicro/stmmac/common.h

+14 −0
Original line number Diff line number Diff line
@@ -530,6 +530,20 @@ struct dma_features { 
#define STMMAC_DEFAULT_TWT_LS	0x1E

#define STMMAC_ET_MAX		0xFFFFF



/* Common LPI register bits */

#define LPI_CTRL_STATUS_LPITCSE	BIT(21)	/* LPI Tx Clock Stop Enable, gmac4, xgmac2 only */

#define LPI_CTRL_STATUS_LPIATE	BIT(20)	/* LPI Timer Enable, gmac4 only */

#define LPI_CTRL_STATUS_LPITXA	BIT(19)	/* Enable LPI TX Automate */

#define LPI_CTRL_STATUS_PLSEN	BIT(18)	/* Enable PHY Link Status */

#define LPI_CTRL_STATUS_PLS	BIT(17)	/* PHY Link Status */

#define LPI_CTRL_STATUS_LPIEN	BIT(16)	/* LPI Enable */

#define LPI_CTRL_STATUS_RLPIST	BIT(9)	/* Receive LPI state, gmac1000 only? */

#define LPI_CTRL_STATUS_TLPIST	BIT(8)	/* Transmit LPI state, gmac1000 only? */

#define LPI_CTRL_STATUS_RLPIEX	BIT(3)	/* Receive LPI Exit */

#define LPI_CTRL_STATUS_RLPIEN	BIT(2)	/* Receive LPI Entry */

#define LPI_CTRL_STATUS_TLPIEX	BIT(1)	/* Transmit LPI Exit */

#define LPI_CTRL_STATUS_TLPIEN	BIT(0)	/* Transmit LPI Entry */



#define STMMAC_CHAIN_MODE	0x1

#define STMMAC_RING_MODE	0x2

drivers/net/ethernet/stmicro/stmmac/dwmac1000.h

+1 −12
Original line number Diff line number Diff line
@@ -59,22 +59,11 @@ enum power_event { 
/* Energy Efficient Ethernet (EEE)

 *

 * LPI status, timer and control register offset

 * For LPI control and status bit definitions, see common.h.

 */

#define LPI_CTRL_STATUS	0x0030

#define LPI_TIMER_CTRL	0x0034



/* LPI control and status defines */

#define LPI_CTRL_STATUS_LPITXA	0x00080000	/* Enable LPI TX Automate */

#define LPI_CTRL_STATUS_PLSEN	0x00040000	/* Enable PHY Link Status */

#define LPI_CTRL_STATUS_PLS	0x00020000	/* PHY Link Status */

#define LPI_CTRL_STATUS_LPIEN	0x00010000	/* LPI Enable */

#define LPI_CTRL_STATUS_RLPIST	0x00000200	/* Receive LPI state */

#define LPI_CTRL_STATUS_TLPIST	0x00000100	/* Transmit LPI state */

#define LPI_CTRL_STATUS_RLPIEX	0x00000008	/* Receive LPI Exit */

#define LPI_CTRL_STATUS_RLPIEN	0x00000004	/* Receive LPI Entry */

#define LPI_CTRL_STATUS_TLPIEX	0x00000002	/* Transmit LPI Exit */

#define LPI_CTRL_STATUS_TLPIEN	0x00000001	/* Transmit LPI Entry */



/* GMAC HW ADDR regs */

#define GMAC_ADDR_HIGH(reg)	((reg > 15) ? 0x00000800 + (reg - 16) * 8 : \

				 0x00000040 + (reg * 8))

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

+1 −11
Original line number Diff line number Diff line
@@ -177,23 +177,13 @@ enum power_event { 
/* Energy Efficient Ethernet (EEE) for GMAC4

 *

 * LPI status, timer and control register offset

 * For LPI control and status bit definitions, see common.h.

 */

#define GMAC4_LPI_CTRL_STATUS	0xd0

#define GMAC4_LPI_TIMER_CTRL	0xd4

#define GMAC4_LPI_ENTRY_TIMER	0xd8

#define GMAC4_MAC_ONEUS_TIC_COUNTER	0xdc



/* LPI control and status defines */

#define GMAC4_LPI_CTRL_STATUS_LPITCSE	BIT(21)	/* LPI Tx Clock Stop Enable */

#define GMAC4_LPI_CTRL_STATUS_LPIATE	BIT(20) /* LPI Timer Enable */

#define GMAC4_LPI_CTRL_STATUS_LPITXA	BIT(19)	/* Enable LPI TX Automate */

#define GMAC4_LPI_CTRL_STATUS_PLS	BIT(17) /* PHY Link Status */

#define GMAC4_LPI_CTRL_STATUS_LPIEN	BIT(16)	/* LPI Enable */

#define GMAC4_LPI_CTRL_STATUS_RLPIEX	BIT(3) /* Receive LPI Exit */

#define GMAC4_LPI_CTRL_STATUS_RLPIEN	BIT(2) /* Receive LPI Entry */

#define GMAC4_LPI_CTRL_STATUS_TLPIEX	BIT(1) /* Transmit LPI Exit */

#define GMAC4_LPI_CTRL_STATUS_TLPIEN	BIT(0) /* Transmit LPI Entry */



/* MAC Debug bitmap */

#define GMAC_DEBUG_TFCSTS_MASK		GENMASK(18, 17)

#define GMAC_DEBUG_TFCSTS_SHIFT		17

drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c

+14 −14
Original line number Diff line number Diff line
@@ -387,11 +387,11 @@ static void dwmac4_set_eee_mode(struct mac_device_info *hw, 
	 * state.

	 */

	value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);

	value &= ~GMAC4_LPI_CTRL_STATUS_LPIATE;

	value |= GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA;

	value &= ~LPI_CTRL_STATUS_LPIATE;

	value |= LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA;



	if (en_tx_lpi_clockgating)

		value |= GMAC4_LPI_CTRL_STATUS_LPITCSE;

		value |= LPI_CTRL_STATUS_LPITCSE;



	writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);

}
@@ -402,8 +402,8 @@ static void dwmac4_reset_eee_mode(struct mac_device_info *hw) 
	u32 value;



	value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);

	value &= ~(GMAC4_LPI_CTRL_STATUS_LPIATE | GMAC4_LPI_CTRL_STATUS_LPIEN |

		   GMAC4_LPI_CTRL_STATUS_LPITXA);

	value &= ~(LPI_CTRL_STATUS_LPIATE | LPI_CTRL_STATUS_LPIEN |

		   LPI_CTRL_STATUS_LPITXA);

	writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);

}
@@ -415,9 +415,9 @@ static void dwmac4_set_eee_pls(struct mac_device_info *hw, int link) 
	value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);



	if (link)

		value |= GMAC4_LPI_CTRL_STATUS_PLS;

		value |= LPI_CTRL_STATUS_PLS;

	else

		value &= ~GMAC4_LPI_CTRL_STATUS_PLS;

		value &= ~LPI_CTRL_STATUS_PLS;



	writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);

}
@@ -433,12 +433,12 @@ static void dwmac4_set_eee_lpi_entry_timer(struct mac_device_info *hw, u32 et) 


	/* Enable/disable LPI entry timer */

	regval = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);

	regval |= GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA;

	regval |= LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA;



	if (et)

		regval |= GMAC4_LPI_CTRL_STATUS_LPIATE;

		regval |= LPI_CTRL_STATUS_LPIATE;

	else

		regval &= ~GMAC4_LPI_CTRL_STATUS_LPIATE;

		regval &= ~LPI_CTRL_STATUS_LPIATE;



	writel(regval, ioaddr + GMAC4_LPI_CTRL_STATUS);

}
@@ -851,17 +851,17 @@ static int dwmac4_irq_status(struct mac_device_info *hw, 
		/* Clear LPI interrupt by reading MAC_LPI_Control_Status */

		u32 status = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);



		if (status & GMAC4_LPI_CTRL_STATUS_TLPIEN) {

		if (status & LPI_CTRL_STATUS_TLPIEN) {

			ret |= CORE_IRQ_TX_PATH_IN_LPI_MODE;

			x->irq_tx_path_in_lpi_mode_n++;

		}

		if (status & GMAC4_LPI_CTRL_STATUS_TLPIEX) {

		if (status & LPI_CTRL_STATUS_TLPIEX) {

			ret |= CORE_IRQ_TX_PATH_EXIT_LPI_MODE;

			x->irq_tx_path_exit_lpi_mode_n++;

		}

		if (status & GMAC4_LPI_CTRL_STATUS_RLPIEN)

		if (status & LPI_CTRL_STATUS_RLPIEN)

			x->irq_rx_path_in_lpi_mode_n++;

		if (status & GMAC4_LPI_CTRL_STATUS_RLPIEX)

		if (status & LPI_CTRL_STATUS_RLPIEX)

			x->irq_rx_path_exit_lpi_mode_n++;

	}

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

+1 −8
Original line number Diff line number Diff line
@@ -112,14 +112,7 @@ 
#define XGMAC_MGKPKTEN			BIT(1)

#define XGMAC_PWRDWN			BIT(0)

#define XGMAC_LPI_CTRL			0x000000d0

#define XGMAC_TXCGE			BIT(21)

#define XGMAC_LPITXA			BIT(19)

#define XGMAC_PLS			BIT(17)

#define XGMAC_LPITXEN			BIT(16)

#define XGMAC_RLPIEX			BIT(3)

#define XGMAC_RLPIEN			BIT(2)

#define XGMAC_TLPIEX			BIT(1)

#define XGMAC_TLPIEN			BIT(0)

/* For definitions, see LPI_CTRL_STATUS_xxx in common.h */

#define XGMAC_LPI_TIMER_CTRL		0x000000d4

#define XGMAC_HW_FEATURE0		0x0000011c

#define XGMAC_HWFEAT_EDMA		BIT(31)