Commit 6e5b72ac authored by Roman Li's avatar Roman Li Committed by Alex Deucher
Browse files

drm/amd/display: Add DML support for dcn42 



DML support for DCN 4.2

Acked-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: default avatarRoman Li <Roman.Li@amd.com>
Signed-off-by: default avatarAlex Hung <alex.hung@amd.com>
Tested-by: default avatarDan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5b880e37

drivers/gpu/drm/amd/display/dc/dml2_0/Makefile

+3 −0
Original line number Diff line number Diff line
@@ -90,6 +90,7 @@ CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.o := $(dml2 
CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.o := $(dml2_ccflags)

CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.o := $(dml2_ccflags)

CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.o := $(dml2_ccflags)

CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn42.o := $(dml2_ccflags)

CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.o := $(dml2_ccflags)

CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.o := $(dml2_ccflags)

CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.o := $(dml2_ccflags)
@@ -107,6 +108,7 @@ CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.o := $(d 
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.o := $(dml2_rcflags)

CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.o := $(dml2_rcflags)

CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.o := $(dml2_rcflags)

CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn42.o := $(dml2_rcflags)

CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.o := $(dml2_rcflags)

CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.o := $(dml2_rcflags)

CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.o := $(dml2_rcflags)
@@ -124,6 +126,7 @@ DML21 += src/dml2_core/dml2_core_dcn4_calcs.o 
DML21 += src/dml2_dpmm/dml2_dpmm_dcn4.o

DML21 += src/dml2_dpmm/dml2_dpmm_factory.o

DML21 += src/dml2_mcg/dml2_mcg_dcn4.o

DML21 += src/dml2_mcg/dml2_mcg_dcn42.o

DML21 += src/dml2_mcg/dml2_mcg_factory.o

DML21 += src/dml2_pmo/dml2_pmo_dcn3.o

DML21 += src/dml2_pmo/dml2_pmo_factory.o

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

+13 −0
Original line number Diff line number Diff line
@@ -45,6 +45,9 @@ static enum dml2_project_id dml21_dcn_revision_to_dml2_project_id(enum dce_versi 
	case DCN_VERSION_4_01:

		project_id = dml2_project_dcn4x_stage2_auto_drr_svp;

		break;

	case DCN_VERSION_4_2:

		project_id = dml2_project_dcn42;

		break;

	default:

		project_id = dml2_project_invalid;

		DC_ERR("unsupported dcn version for DML21!");
@@ -615,6 +618,13 @@ static void populate_dml21_plane_config_from_plane_state(struct dml2_context *dm 
		case DC_CM2_GPU_MEM_SIZE_171717:

			plane->tdlut.tdlut_width_mode = dml2_tdlut_width_17_cube;

			break;

		case DC_CM2_GPU_MEM_SIZE_333333:

			plane->tdlut.tdlut_width_mode = dml2_tdlut_width_33_cube;

			break;

		// handling when use case and HW support available

		case DC_CM2_GPU_MEM_SIZE_454545:

		case DC_CM2_GPU_MEM_SIZE_656565:

			break;

		case DC_CM2_GPU_MEM_SIZE_TRANSFORMED:

		default:

			//plane->tdlut.tdlut_width_mode = dml2_tdlut_width_flatten; // dml2_tdlut_width_flatten undefined
@@ -824,6 +834,9 @@ void dml21_copy_clocks_to_dc_state(struct dml2_context *in_ctx, struct dc_state 
	context->bw_ctx.bw.dcn.clk.subvp_prefetch_fclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.svp_prefetch_no_throttle.fclk_khz;

	context->bw_ctx.bw.dcn.clk.stutter_efficiency.base_efficiency = in_ctx->v21.mode_programming.programming->stutter.base_percent_efficiency;

	context->bw_ctx.bw.dcn.clk.stutter_efficiency.low_power_efficiency = in_ctx->v21.mode_programming.programming->stutter.low_power_percent_efficiency;

	context->bw_ctx.bw.dcn.clk.stutter_efficiency.z8_stutter_efficiency = in_ctx->v21.mode_programming.programming->informative.power_management.z8.stutter_efficiency;

	context->bw_ctx.bw.dcn.clk.stutter_efficiency.z8_stutter_period = in_ctx->v21.mode_programming.programming->informative.power_management.z8.stutter_period;

	context->bw_ctx.bw.dcn.clk.zstate_support = in_ctx->v21.mode_programming.programming->z8_stutter.supported_in_blank; /*ignore meets_eco since it is not used*/

}



static struct dml2_dchub_watermark_regs *wm_set_index_to_dc_wm_set(union dcn_watermark_set *watermarks, const enum dml2_dchub_watermark_reg_set_index wm_index)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h

+1 −0
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ enum dml2_project_id { 
	dml2_project_dcn4x_stage1,

	dml2_project_dcn4x_stage2,

	dml2_project_dcn4x_stage2_auto_drr_svp,

	dml2_project_dcn42,

};



enum dml2_pstate_change_support {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c

+111 −0
Original line number Diff line number Diff line
@@ -78,6 +78,86 @@ struct dml2_core_ip_params core_dcn4_ip_caps_base = { 
	.subvp_swath_height_margin_lines = 16,

};



struct dml2_core_ip_params core_dcn42_ip_caps_base = {

	.vblank_nom_default_us = 668,

	.remote_iommu_outstanding_translations = 256,

	.rob_buffer_size_kbytes = 64,

	.config_return_buffer_size_in_kbytes = 1792,

	.config_return_buffer_segment_size_in_kbytes = 64,

	.compressed_buffer_segment_size_in_kbytes = 64,

	.dpte_buffer_size_in_pte_reqs_luma = 68,

	.dpte_buffer_size_in_pte_reqs_chroma = 36,

	.pixel_chunk_size_kbytes = 8,

	.alpha_pixel_chunk_size_kbytes = 4,

	.min_pixel_chunk_size_bytes = 1024,

	.writeback_chunk_size_kbytes = 8,

	.line_buffer_size_bits = 1171920,

	.max_line_buffer_lines = 32,

	.writeback_interface_buffer_size_kbytes = 90,



	//Number of pipes after DCN Pipe harvesting

	.max_num_dpp = 4,

	.max_num_otg = 4,

	.max_num_opp = 4,

	.max_num_wb = 1,

	.max_dchub_pscl_bw_pix_per_clk = 4,

	.max_pscl_lb_bw_pix_per_clk = 2,

	.max_lb_vscl_bw_pix_per_clk = 4,

	.max_vscl_hscl_bw_pix_per_clk = 4,

	.max_hscl_ratio = 6,

	.max_vscl_ratio = 6,

	.max_hscl_taps = 8,

	.max_vscl_taps = 8,

	.dispclk_ramp_margin_percent = 1,

	.dppclk_delay_subtotal = 47,

	.dppclk_delay_scl = 50,

	.dppclk_delay_scl_lb_only = 16,

	.dppclk_delay_cnvc_formatter = 28,

	.dppclk_delay_cnvc_cursor = 6,

	.cursor_buffer_size = 42,

	.cursor_chunk_size = 2,

	.dispclk_delay_subtotal = 125,

	.max_inter_dcn_tile_repeaters = 8,

	.writeback_max_hscl_ratio = 1,

	.writeback_max_vscl_ratio = 1,

	.writeback_min_hscl_ratio = 1,

	.writeback_min_vscl_ratio = 1,

	.writeback_max_hscl_taps = 1,

	.writeback_max_vscl_taps = 1,

	.writeback_line_buffer_buffer_size = 0,

	.num_dsc = 4,

	.maximum_dsc_bits_per_component = 12,

	.maximum_pixels_per_line_per_dsc_unit = 5760,

	.dsc422_native_support = true,

	.dcc_supported = true,

	.ptoi_supported = false,



	.cursor_64bpp_support = true,

	.dynamic_metadata_vm_enabled = false,



	.max_num_hdmi_frl_outputs = 0,

	.max_num_dp2p0_outputs = 2,

	.max_num_dp2p0_streams = 4,

	.imall_supported = 1,

	.max_flip_time_us = 110,

	.max_flip_time_lines = 50,

	.words_per_channel = 16,



	.subvp_fw_processing_delay_us = 15,

	.subvp_pstate_allow_width_us = 20,

	.subvp_swath_height_margin_lines = 16,



	.dcn_mrq_present = 1,

	.zero_size_buffer_entries = 512,

	.compbuf_reserved_space_zs = 64,

	.dcc_meta_buffer_size_bytes = 6272,

	.meta_chunk_size_kbytes = 2,

	.min_meta_chunk_size_bytes = 256,



	.dchub_arb_to_ret_delay = 102,

	.hostvm_mode = 1,

};



static void patch_ip_caps_with_explicit_ip_params(struct dml2_ip_capabilities *ip_caps, const struct dml2_core_ip_params *ip_params)

{

	ip_caps->pipe_count = ip_params->max_num_dpp;
@@ -153,6 +233,37 @@ bool core_dcn4_initialize(struct dml2_core_initialize_in_out *in_out) 
	return true;

}



bool core_dcn42_initialize(struct dml2_core_initialize_in_out *in_out)

{

	struct dml2_core_instance *core = in_out->instance;



	if (!in_out->minimum_clock_table)

		return false;

	else

		core->minimum_clock_table = in_out->minimum_clock_table;



	if (in_out->explicit_ip_bb && in_out->explicit_ip_bb_size > 0) {

		memcpy(&core->clean_me_up.mode_lib.ip, in_out->explicit_ip_bb, in_out->explicit_ip_bb_size);



		// FIXME_STAGE2:

		// DV still uses stage1 ip_param_st for each variant, need to patch the ip_caps with ip_param info

		// Should move DV to use ip_caps but need move more overrides to ip_caps

		patch_ip_caps_with_explicit_ip_params(in_out->ip_caps, in_out->explicit_ip_bb);

		core->clean_me_up.mode_lib.ip.subvp_pstate_allow_width_us = core_dcn4_ip_caps_base.subvp_pstate_allow_width_us;

		core->clean_me_up.mode_lib.ip.subvp_fw_processing_delay_us = core_dcn4_ip_caps_base.subvp_pstate_allow_width_us;

		core->clean_me_up.mode_lib.ip.subvp_swath_height_margin_lines = core_dcn4_ip_caps_base.subvp_swath_height_margin_lines;

	} else {

		memcpy(&core->clean_me_up.mode_lib.ip, &core_dcn42_ip_caps_base, sizeof(struct dml2_core_ip_params));

		patch_ip_params_with_ip_caps(&core->clean_me_up.mode_lib.ip, in_out->ip_caps);

		core->clean_me_up.mode_lib.ip.imall_supported = false;

	}



	memcpy(&core->clean_me_up.mode_lib.soc, in_out->soc_bb, sizeof(struct dml2_soc_bb));

	memcpy(&core->clean_me_up.mode_lib.ip_caps, in_out->ip_caps, sizeof(struct dml2_ip_capabilities));



	return true;

}



static void create_phantom_stream_from_main_stream(struct dml2_stream_parameters *phantom, const struct dml2_stream_parameters *main,

	const struct dml2_implicit_svp_meta *meta)

{

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.h

+1 −0
Original line number Diff line number Diff line
@@ -5,6 +5,7 @@ 
#ifndef __DML2_CORE_DCN4_H__

#define __DML2_CORE_DCN4_H__

bool core_dcn4_initialize(struct dml2_core_initialize_in_out *in_out);

bool core_dcn42_initialize(struct dml2_core_initialize_in_out *in_out);

bool core_dcn4_mode_support(struct dml2_core_mode_support_in_out *in_out);

bool core_dcn4_mode_programming(struct dml2_core_mode_programming_in_out *in_out);

bool core_dcn4_populate_informative(struct dml2_core_populate_informative_in_out *in_out);