Commit 6e89ef8f authored by Devi Priya's avatar Devi Priya Committed by Bjorn Andersson
Browse files

clk: qcom: gcc-ipq9574: Add support for gpll0_out_aux clock 



Add support for gpll0_out_aux clock which acts as the parent for
certain networking subsystem (nss) clocks.

Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarDevi Priya <quic_devipriy@quicinc.com>
Signed-off-by: default avatarManikanta Mylavarapu <quic_mmanikan@quicinc.com>
Link: https://lore.kernel.org/r/20250313110359.242491-3-quic_mmanikan@quicinc.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 0139f7d4

drivers/clk/qcom/gcc-ipq9574.c

+15 −0
Original line number Diff line number Diff line
@@ -108,6 +108,20 @@ static struct clk_alpha_pll_postdiv gpll0 = { 
	},

};



static struct clk_alpha_pll_postdiv gpll0_out_aux = {

	.offset = 0x20000,

	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],

	.width = 4,

	.clkr.hw.init = &(const struct clk_init_data) {

		.name = "gpll0_out_aux",

		.parent_hws = (const struct clk_hw *[]) {

			&gpll0_main.clkr.hw

		},

		.num_parents = 1,

		.ops = &clk_alpha_pll_postdiv_ro_ops,

	},

};



static struct clk_alpha_pll gpll4_main = {

	.offset = 0x22000,

	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
@@ -3896,6 +3910,7 @@ static struct clk_regmap *gcc_ipq9574_clks[] = { 
	[GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,

	[GCC_PCIE2_PIPE_CLK] = &gcc_pcie2_pipe_clk.clkr,

	[GCC_PCIE3_PIPE_CLK] = &gcc_pcie3_pipe_clk.clkr,

	[GPLL0_OUT_AUX] = &gpll0_out_aux.clkr,

};



static const struct qcom_reset_map gcc_ipq9574_resets[] = {