Unverified Commit 6eb0168d authored by Michal Wajdeczko's avatar Michal Wajdeczko Committed by Rodrigo Vivi
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drm/xe/memirq: Update interrupt handler logic 



To workaround some corner case hardware limitations, new programming
note for the memory based interrupt handler suggests to assume that
some status bytes, like GT_MI_USER_INTERRUPT and GUC_INTR_GUC2HOST,
are always set. Update our interrupt handler to follow the new rules.

Bspec: 53672
Fixes: a6581ebe ("drm/xe/vf: Introduce Memory Based Interrupts Handler")
Signed-off-by: default avatarMichal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: default avatarMichał Winiarski <michal.winiarski@intel.com>
Link: https://patch.msgid.link/20260511172838.2299-2-michal.wajdeczko@intel.com


(cherry picked from commit 284f4cae4579eed9dd4406f18a6c1becc69f8931)
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent 5200f5f4

drivers/gpu/drm/xe/xe_memirq.c

+22 −4
Original line number Diff line number Diff line
@@ -427,12 +427,24 @@ static bool memirq_received(struct xe_memirq *memirq, struct iosys_map *vector, 
	return __memirq_received(memirq, vector, offset, name, true);

}



static void memirq_assume_received(struct xe_memirq *memirq, const char *source,

				   u16 offset, const char *status)

{

	memirq_debug(memirq, "ASSUME %s %s(%u)\n", source, status, offset);

}



static void memirq_dispatch_engine(struct xe_memirq *memirq, struct iosys_map *status,

				   struct xe_hw_engine *hwe)

{

	memirq_debug(memirq, "STATUS %s %*ph\n", hwe->name, 16, status->vaddr);



	if (memirq_received(memirq, status, ilog2(GT_MI_USER_INTERRUPT), hwe->name))

	/*

	 * The programming note says to assume that GT_MI_USER_INTERRUPT is always

	 * set. Check and clear related status byte just for a debug.

	 */

	if (IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEMIRQ) &&

	    !memirq_received(memirq, status, ilog2(GT_MI_USER_INTERRUPT), hwe->name))

		memirq_assume_received(memirq, hwe->name, ilog2(GT_MI_USER_INTERRUPT), "USER");

	xe_hw_engine_handle_irq(hwe, GT_MI_USER_INTERRUPT);

}
@@ -443,7 +455,13 @@ static void memirq_dispatch_guc(struct xe_memirq *memirq, struct iosys_map *stat 


	memirq_debug(memirq, "STATUS %s %*ph\n", name, 16, status->vaddr);



	if (memirq_received(memirq, status, ilog2(GUC_INTR_GUC2HOST), name))

	/*

	 * The programming note says to assume that GUC_INTR_GUC2HOST is always

	 * set. Check and clear related status byte just for a debug.

	 */

	if (IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEMIRQ) &&

	    !memirq_received(memirq, status, ilog2(GUC_INTR_GUC2HOST), name))

		memirq_assume_received(memirq, name, ilog2(GUC_INTR_GUC2HOST), "GUC2HOST");

	xe_guc_irq_handler(guc, GUC_INTR_GUC2HOST);



	/*