Commit 6ed85ea1 authored by Srinivas Kandagatla's avatar Srinivas Kandagatla Committed by Vinod Koul
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soundwire: qcom: prepare for v3.x 



cleanup the register layout structs to prepare for adding new 3.x
controller support.

Signed-off-by: default avatarSrinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>
Tested-by: Alexey Klimov <alexey.klimov@linaro.org> # sm8550
Link: https://patch.msgid.link/20250912083225.228778-6-srinivas.kandagatla@oss.qualcomm.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 9e53a66a

drivers/soundwire/qcom.c

+56 −21
Original line number Diff line number Diff line
@@ -99,14 +99,15 @@ 
#define SWRM_MCP_SLV_STATUS					0x1090

#define SWRM_MCP_SLV_STATUS_MASK				GENMASK(1, 0)

#define SWRM_MCP_SLV_STATUS_SZ					2

#define SWRM_DP_PORT_CTRL_BANK(n, m)	(0x1124 + 0x100 * (n - 1) + 0x40 * m)

#define SWRM_DP_PORT_CTRL_2_BANK(n, m)	(0x1128 + 0x100 * (n - 1) + 0x40 * m)

#define SWRM_DP_BLOCK_CTRL_1(n)		(0x112C + 0x100 * (n - 1))

#define SWRM_DP_BLOCK_CTRL2_BANK(n, m)	(0x1130 + 0x100 * (n - 1) + 0x40 * m)

#define SWRM_DP_PORT_HCTRL_BANK(n, m)	(0x1134 + 0x100 * (n - 1) + 0x40 * m)

#define SWRM_DP_BLOCK_CTRL3_BANK(n, m)	(0x1138 + 0x100 * (n - 1) + 0x40 * m)

#define SWRM_DP_SAMPLECTRL2_BANK(n, m)	(0x113C + 0x100 * (n - 1) + 0x40 * m)

#define SWRM_DIN_DPn_PCM_PORT_CTRL(n)	(0x1054 + 0x100 * (n - 1))



#define SWRM_DPn_PORT_CTRL_BANK(offset, n, m)	(offset + 0x100 * (n - 1) + 0x40 * m)

#define SWRM_DPn_PORT_CTRL_2_BANK(offset, n, m)	(offset + 0x100 * (n - 1) + 0x40 * m)

#define SWRM_DPn_BLOCK_CTRL_1(offset, n)	(offset + 0x100 * (n - 1))

#define SWRM_DPn_BLOCK_CTRL2_BANK(offset, n, m)	(offset + 0x100 * (n - 1) + 0x40 * m)

#define SWRM_DPn_PORT_HCTRL_BANK(offset,  n, m)	(offset + 0x100 * (n - 1) + 0x40 * m)

#define SWRM_DPn_BLOCK_CTRL3_BANK(offset, n, m)	(offset + 0x100 * (n - 1) + 0x40 * m)

#define SWRM_DPn_SAMPLECTRL2_BANK(offset, n, m)	(offset + 0x100 * (n - 1) + 0x40 * m)



#define SWR_V1_3_MSTR_MAX_REG_ADDR				0x1740

#define SWR_V2_0_MSTR_MAX_REG_ADDR				0x50ac
@@ -171,6 +172,13 @@ enum { 
	SWRM_REG_CMD_FIFO_RD_CMD,

	SWRM_REG_CMD_FIFO_STATUS,

	SWRM_REG_CMD_FIFO_RD_FIFO_ADDR,

	SWRM_OFFSET_DP_PORT_CTRL_BANK,

	SWRM_OFFSET_DP_PORT_CTRL_2_BANK,

	SWRM_OFFSET_DP_BLOCK_CTRL_1,

	SWRM_OFFSET_DP_BLOCK_CTRL2_BANK,

	SWRM_OFFSET_DP_PORT_HCTRL_BANK,

	SWRM_OFFSET_DP_BLOCK_CTRL3_BANK,

	SWRM_OFFSET_DP_SAMPLECTRL2_BANK,

};



struct qcom_swrm_ctrl {
@@ -230,6 +238,13 @@ static const unsigned int swrm_v1_3_reg_layout[] = { 
	[SWRM_REG_CMD_FIFO_RD_CMD] = SWRM_V1_3_CMD_FIFO_RD_CMD,

	[SWRM_REG_CMD_FIFO_STATUS] = SWRM_V1_3_CMD_FIFO_STATUS,

	[SWRM_REG_CMD_FIFO_RD_FIFO_ADDR] = SWRM_V1_3_CMD_FIFO_RD_FIFO_ADDR,

	[SWRM_OFFSET_DP_PORT_CTRL_BANK]		= 0x1124,

	[SWRM_OFFSET_DP_PORT_CTRL_2_BANK]	= 0x1128,

	[SWRM_OFFSET_DP_BLOCK_CTRL_1]		= 0x112c,

	[SWRM_OFFSET_DP_BLOCK_CTRL2_BANK]	= 0x1130,

	[SWRM_OFFSET_DP_PORT_HCTRL_BANK]	= 0x1134,

	[SWRM_OFFSET_DP_BLOCK_CTRL3_BANK]	= 0x1138,

	[SWRM_OFFSET_DP_SAMPLECTRL2_BANK]	= 0x113c,

};



static const struct qcom_swrm_data swrm_v1_3_data = {
@@ -264,6 +279,13 @@ static const unsigned int swrm_v2_0_reg_layout[] = { 
	[SWRM_REG_CMD_FIFO_RD_CMD] = SWRM_V2_0_CMD_FIFO_RD_CMD,

	[SWRM_REG_CMD_FIFO_STATUS] = SWRM_V2_0_CMD_FIFO_STATUS,

	[SWRM_REG_CMD_FIFO_RD_FIFO_ADDR] = SWRM_V2_0_CMD_FIFO_RD_FIFO_ADDR,

	[SWRM_OFFSET_DP_PORT_CTRL_BANK]		= 0x1124,

	[SWRM_OFFSET_DP_PORT_CTRL_2_BANK]	= 0x1128,

	[SWRM_OFFSET_DP_BLOCK_CTRL_1]		= 0x112c,

	[SWRM_OFFSET_DP_BLOCK_CTRL2_BANK]	= 0x1130,

	[SWRM_OFFSET_DP_PORT_HCTRL_BANK]	= 0x1134,

	[SWRM_OFFSET_DP_BLOCK_CTRL3_BANK]	= 0x1138,

	[SWRM_OFFSET_DP_SAMPLECTRL2_BANK]	= 0x113c,

};



static const struct qcom_swrm_data swrm_v2_0_data = {
@@ -964,10 +986,10 @@ static int qcom_swrm_port_params(struct sdw_bus *bus, 
				 unsigned int bank)

{

	struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);

	u32 offset = ctrl->reg_layout[SWRM_OFFSET_DP_BLOCK_CTRL_1];



	return ctrl->reg_write(ctrl, SWRM_DP_BLOCK_CTRL_1(p_params->num),

	return ctrl->reg_write(ctrl, SWRM_DPn_BLOCK_CTRL_1(offset, p_params->num),

				p_params->bps - 1);



}



static int qcom_swrm_transport_params(struct sdw_bus *bus,
@@ -977,9 +999,11 @@ static int qcom_swrm_transport_params(struct sdw_bus *bus, 
	struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);

	struct qcom_swrm_port_config *pcfg;

	u32 value;

	int reg = SWRM_DP_PORT_CTRL_BANK((params->port_num), bank);

	int reg, offset = ctrl->reg_layout[SWRM_OFFSET_DP_PORT_CTRL_BANK];

	int ret;



	reg = SWRM_DPn_PORT_CTRL_BANK(offset, params->port_num, bank);



	pcfg = &ctrl->pconfig[params->port_num];



	value = pcfg->off1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT;
@@ -991,15 +1015,19 @@ static int qcom_swrm_transport_params(struct sdw_bus *bus, 
		goto err;



	if (pcfg->si > 0xff) {

		offset = ctrl->reg_layout[SWRM_OFFSET_DP_SAMPLECTRL2_BANK];

		value = (pcfg->si >> 8) & 0xff;

		reg = SWRM_DP_SAMPLECTRL2_BANK(params->port_num, bank);

		reg = SWRM_DPn_SAMPLECTRL2_BANK(offset, params->port_num, bank);



		ret = ctrl->reg_write(ctrl, reg, value);

		if (ret)

			goto err;

	}



	if (pcfg->lane_control != SWR_INVALID_PARAM) {

		reg = SWRM_DP_PORT_CTRL_2_BANK(params->port_num, bank);

		offset = ctrl->reg_layout[SWRM_OFFSET_DP_PORT_CTRL_2_BANK];

		reg = SWRM_DPn_PORT_CTRL_2_BANK(offset, params->port_num, bank);



		value = pcfg->lane_control;

		ret = ctrl->reg_write(ctrl, reg, value);

		if (ret)
@@ -1007,20 +1035,23 @@ static int qcom_swrm_transport_params(struct sdw_bus *bus, 
	}



	if (pcfg->blk_group_count != SWR_INVALID_PARAM) {

		reg = SWRM_DP_BLOCK_CTRL2_BANK(params->port_num, bank);

		offset = ctrl->reg_layout[SWRM_OFFSET_DP_BLOCK_CTRL2_BANK];



		reg = SWRM_DPn_BLOCK_CTRL2_BANK(offset, params->port_num, bank);



		value = pcfg->blk_group_count;

		ret = ctrl->reg_write(ctrl, reg, value);

		if (ret)

			goto err;

	}



	if (pcfg->hstart != SWR_INVALID_PARAM

			&& pcfg->hstop != SWR_INVALID_PARAM) {

		reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank);

	offset = ctrl->reg_layout[SWRM_OFFSET_DP_PORT_HCTRL_BANK];

	reg = SWRM_DPn_PORT_HCTRL_BANK(offset, params->port_num, bank);



	if (pcfg->hstart != SWR_INVALID_PARAM && pcfg->hstop != SWR_INVALID_PARAM) {

		value = (pcfg->hstop << 4) | pcfg->hstart;

		ret = ctrl->reg_write(ctrl, reg, value);

	} else {

		reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank);

		value = (SWR_HSTOP_MAX_VAL << 4) | SWR_HSTART_MIN_VAL;

		ret = ctrl->reg_write(ctrl, reg, value);

	}
@@ -1029,7 +1060,8 @@ static int qcom_swrm_transport_params(struct sdw_bus *bus, 
		goto err;



	if (pcfg->bp_mode != SWR_INVALID_PARAM) {

		reg = SWRM_DP_BLOCK_CTRL3_BANK(params->port_num, bank);

		offset = ctrl->reg_layout[SWRM_OFFSET_DP_BLOCK_CTRL3_BANK];

		reg = SWRM_DPn_BLOCK_CTRL3_BANK(offset, params->port_num, bank);

		ret = ctrl->reg_write(ctrl, reg, pcfg->bp_mode);

	}
@@ -1041,9 +1073,12 @@ static int qcom_swrm_port_enable(struct sdw_bus *bus, 
				 struct sdw_enable_ch *enable_ch,

				 unsigned int bank)

{

	u32 reg = SWRM_DP_PORT_CTRL_BANK(enable_ch->port_num, bank);

	u32 reg;

	struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);

	u32 val;

	u32 offset = ctrl->reg_layout[SWRM_OFFSET_DP_PORT_CTRL_BANK];



	reg = SWRM_DPn_PORT_CTRL_BANK(offset, enable_ch->port_num, bank);



	ctrl->reg_read(ctrl, reg, &val);