Unverified Commit 6f0fce21 authored by Mark Brown's avatar Mark Brown
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ASoC: ti: davinci-mcasp: Add asynchronous mode

Merge series from Sen Wang <sen@ti.com>:

This series adds asynchronous mode support to the McASP driver, which
enables independent configuration of bitclocks, frame sync, and audio
configurations between tx(playback) and rx(record). And achieves
simultaneous playback & record using different audio configurations.

It also adds two clean up patches to the McASP driver that disambiguate
and simplifies the logic which avoids the async enhancement from being
too convoluted to review and analyze.

The implementation is based on vendor documentation and patches tested in
both SK-AM62P-LP (sync mode, McASP slave) and AM62D-EVM
(async mode, McASP master, rx & tx has different TDM configs).
Testing verifies async mode functionality while maintaining backward
compatibility with the default sync mode.

Bootlog and Async mode tests on AM62D-EVM: [0]

[0]: https://gist.github.com/SenWang125/f31f9172b186d414695e37c8b9ef127d
parents 7c2280e5 9db32708
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+66 −5
Original line number Diff line number Diff line
@@ -40,11 +40,33 @@ properties:
  tdm-slots:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      number of channels over one serializer
      the property is ignored in DIT mode
      Number of channels over one serializer. This property
      specifies the TX playback TDM slot count, along with default RX slot count
      if tdm-slots-rx is not specified.
      The property is ignored in DIT mode.
    minimum: 2
    maximum: 32

  tdm-slots-rx:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Number of RX capture channels over one serializer. If specified,
      allows independent RX TDM slot count separate from TX. Requires
      ti,async-mode to be enabled for independent TX/RX clock rates.
      The property is ignored in DIT mode.
    minimum: 2
    maximum: 32

  ti,async-mode:
    description:
      Specify to allow independent TX & RX clocking,
      to enable audio playback & record with different sampling rate,
      and different number of bits per frame.
      if property is omitted, TX and RX will share same bit clock and frame clock signals,
      thus RX need to use same bits per frame and sampling rate as TX in synchronous mode.
      the property is ignored in DIT mode (as DIT is TX-only)
    type: boolean

  serial-dir:
    description:
      A list of serializer configuration
@@ -125,7 +147,21 @@ properties:

  auxclk-fs-ratio:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: ratio of AUCLK and FS rate if applicable
    description:
      Ratio of AUCLK and FS rate if applicable. This property specifies
      the TX ratio, along with default RX ratio if auxclk-fs-ratio-rx
      is not specified.
      When not specified, the inputted system clock frequency via set_sysclk
      callback by the machine driver is used for divider calculation.

  auxclk-fs-ratio-rx:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Ratio of AUCLK and FS rate for RX. If specified, allows
      for a different RX ratio. Requires ti,async-mode to be
      enabled when the ratio differs from auxclk-fs-ratio.
      When not specified, it defaults to the value of auxclk-fs-ratio.
      The property is ignored in DIT mode.

  gpio-controller: true

@@ -170,14 +206,38 @@ allOf:
  - $ref: dai-common.yaml#
  - if:
      properties:
        opmode:
        op-mode:
          enum:
            - 0

    then:
      required:
        - tdm-slots

  - if:
      properties:
        op-mode:
          const: 1
    then:
      properties:
        tdm-slots: false
        tdm-slots-rx: false
        ti,async-mode: false
        auxclk-fs-ratio-rx: false

  - if:
      required:
        - tdm-slots-rx
    then:
      required:
        - ti,async-mode

  - if:
      required:
        - auxclk-fs-ratio-rx
    then:
      required:
        - ti,async-mode

unevaluatedProperties: false

examples:
@@ -190,6 +250,7 @@ examples:
      interrupt-names = "tx", "rx";
      op-mode = <0>;		/* MCASP_IIS_MODE */
      tdm-slots = <2>;
      ti,async-mode;
      dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
      dma-names = "tx", "rx";
      serial-dir = <
+2 −1
Original line number Diff line number Diff line
@@ -59,7 +59,8 @@ struct davinci_mcasp_pdata {
	bool i2s_accurate_sck;

	/* McASP specific fields */
	int tdm_slots;
	int tdm_slots_tx;
	int tdm_slots_rx;
	u8 op_mode;
	u8 dismod;
	u8 num_serializer;
+403 −107

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+10 −0
Original line number Diff line number Diff line
@@ -298,10 +298,20 @@
/* Source of High-frequency transmit/receive clock */
#define MCASP_CLK_HCLK_AHCLK		0 /* AHCLKX/R */
#define MCASP_CLK_HCLK_AUXCLK		1 /* Internal functional clock */
#define MCASP_CLK_HCLK_AHCLK_TXONLY	2 /* AHCLKX for TX only */
#define MCASP_CLK_HCLK_AHCLK_RXONLY	3 /* AHCLKR for RX only */
#define MCASP_CLK_HCLK_AUXCLK_TXONLY	4 /* AUXCLK for TX only */
#define MCASP_CLK_HCLK_AUXCLK_RXONLY	5 /* AUXCLK for RX only */

/* clock divider IDs */
#define MCASP_CLKDIV_AUXCLK		0 /* HCLK divider from AUXCLK */
#define MCASP_CLKDIV_BCLK		1 /* BCLK divider from HCLK */
#define MCASP_CLKDIV_BCLK_FS_RATIO	2 /* to set BCLK FS ration */
#define MCASP_CLKDIV_AUXCLK_TXONLY	3 /* AUXCLK divider for TX only */
#define MCASP_CLKDIV_AUXCLK_RXONLY	4 /* AUXCLK divider for RX only */
#define MCASP_CLKDIV_BCLK_TXONLY	5 /* BCLK divider for TX only */
#define MCASP_CLKDIV_BCLK_RXONLY	6 /* BCLK divider for RX only */
#define MCASP_CLKDIV_BCLK_FS_RATIO_TXONLY 7 /* BCLK/FS ratio for TX only */
#define MCASP_CLKDIV_BCLK_FS_RATIO_RXONLY 8 /* BCLK/FS ratio for RX only*/

#endif	/* DAVINCI_MCASP_H */