Commit 701d1057 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-imx-6.7' of... 

Merge tag 'clk-imx-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx

Pull i.MX clk driver updates from Abel Vesa:

 - Select MXC_CLK when building in the CLK_IMX8QXP
 - Fixes for error handling paths in i.MX8 ACM driver
 - Move the clocks check in i.MX8 ACM driver in order to log any error
 - Drop the unused return value of clk_imx_acm_detach_pm_domains
 - Drop non-existant IMX8MP_CLK_AUDIOMIX_PDM_ROOT clock
 - Fix error handling in i.MX8MQ clock driver
 - Allow a different LCDIF1 clock parent if DT describes it for i.MX6SX
 - Keep the SCU resource table sorted in the i.MX8DXL rsrc driver
 - Move the elcdif PLL clock registration above lcd_clk, as it is its parent
 - Correct some ENET specific clocks for i.MX8DXL platform
 - Drop the VPU_UART and VPUCORE from i.MX8QM as latest HW revision doesn't have them
 - Remove "de-featured" MLB support from i.MX8QM/QXP/DXL platforms
 - Skip registering clocks owned by Cortex-A partition SCU-based platforms
 - Add CAN_1/2 to i.MX8QM and M4_0, PI_0_PWM_0 and PI_0_I2C_0 to i.MX8QXP resources

* tag 'clk-imx-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux:
  clk: imx: imx8qm/qxp: add more resources to whitelist
  clk: imx: scu: ignore clks not owned by Cortex-A partition
  clk: imx8: remove MLB support
  clk: imx: imx8qm-rsrc: drop VPU_UART/VPUCORE
  clk: imx: imx8qxp: correct the enet clocks for i.MX8DXL
  clk: imx: imx8qxp: Fix elcdif_pll clock
  clk: imx: imx8dxl-rsrc: keep sorted in the ascending order
  clk: imx: imx6sx: Allow a different LCDIF1 clock parent
  clk: imx: imx8mq: correct error handling path
  clk: imx8mp: Remove non-existent IMX8MP_CLK_AUDIOMIX_PDM_ROOT
  clk: imx: imx8: Simplify clk_imx_acm_detach_pm_domains()
  clk: imx: imx8: Add a message in case of devm_clk_hw_register_mux_parent_data_table() error
  clk: imx: imx8: Fix an error handling path in imx8_acm_clk_probe()
  clk: imx: imx8: Fix an error handling path if devm_clk_hw_register_mux_parent_data_table() fails
  clk: imx: imx8: Fix an error handling path in clk_imx_acm_attach_pm_domains()
  clk: imx: Select MXC_CLK for CLK_IMX8QXP
parents 0bb80ecc 28388208

drivers/clk/imx/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -96,6 +96,7 @@ config CLK_IMX8QXP 
	depends on (ARCH_MXC && ARM64) || COMPILE_TEST

	depends on IMX_SCU && HAVE_ARM_SMCCC

	select MXC_CLK_SCU

	select MXC_CLK

	help

	  Build the driver for IMX8QXP SCU based clocks.

drivers/clk/imx/clk-imx6sx.c

+11 −3
Original line number Diff line number Diff line
@@ -121,6 +121,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) 
{

	struct device_node *np;

	void __iomem *base;

	bool lcdif1_assigned_clk;



	clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,

					  IMX6SX_CLK_CLK_END), GFP_KERNEL);
@@ -498,9 +499,16 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) 
	clk_set_parent(hws[IMX6SX_CLK_EIM_SLOW_SEL]->clk, hws[IMX6SX_CLK_PLL2_PFD2]->clk);

	clk_set_rate(hws[IMX6SX_CLK_EIM_SLOW]->clk, 132000000);



	/* set parent clock for LCDIF1 pixel clock */

	clk_set_parent(hws[IMX6SX_CLK_LCDIF1_PRE_SEL]->clk, hws[IMX6SX_CLK_PLL5_VIDEO_DIV]->clk);

	clk_set_parent(hws[IMX6SX_CLK_LCDIF1_SEL]->clk, hws[IMX6SX_CLK_LCDIF1_PODF]->clk);

	np = of_find_node_by_path("/soc/bus@2200000/spba-bus@2240000/lcdif@2220000");

	lcdif1_assigned_clk = of_find_property(np, "assigned-clock-parents", NULL);



	/* Set parent clock for LCDIF1 pixel clock if not done via devicetree */

	if (!lcdif1_assigned_clk) {

		clk_set_parent(hws[IMX6SX_CLK_LCDIF1_PRE_SEL]->clk,

			       hws[IMX6SX_CLK_PLL5_VIDEO_DIV]->clk);

		clk_set_parent(hws[IMX6SX_CLK_LCDIF1_SEL]->clk,

			       hws[IMX6SX_CLK_LCDIF1_PODF]->clk);

	}



	/* Set the parent clks of PCIe lvds1 and pcie_axi to be pcie ref, axi */

	if (clk_set_parent(hws[IMX6SX_CLK_LVDS1_SEL]->clk, hws[IMX6SX_CLK_PCIE_REF_125M]->clk))

drivers/clk/imx/clk-imx8-acm.c

+18 −15
Original line number Diff line number Diff line
@@ -77,7 +77,7 @@ struct imx8_acm_priv { 
static const struct clk_parent_data imx8qm_aud_clk_sels[] = {

	{ .fw_name = "aud_rec_clk0_lpcg_clk" },

	{ .fw_name = "aud_rec_clk1_lpcg_clk" },

	{ .fw_name = "mlb_clk" },

	{ .fw_name = "dummy" },

	{ .fw_name = "hdmi_rx_mclk" },

	{ .fw_name = "ext_aud_mclk0" },

	{ .fw_name = "ext_aud_mclk1" },
@@ -103,7 +103,7 @@ static const struct clk_parent_data imx8qm_aud_clk_sels[] = { 
static const struct clk_parent_data imx8qm_mclk_out_sels[] = {

	{ .fw_name = "aud_rec_clk0_lpcg_clk" },

	{ .fw_name = "aud_rec_clk1_lpcg_clk" },

	{ .fw_name = "mlb_clk" },

	{ .fw_name = "dummy" },

	{ .fw_name = "hdmi_rx_mclk" },

	{ .fw_name = "spdif0_rx" },

	{ .fw_name = "spdif1_rx" },
@@ -122,7 +122,7 @@ static const struct clk_parent_data imx8qm_asrc_mux_clk_sels[] = { 
	{ .fw_name = "sai4_rx_bclk" },

	{ .fw_name = "sai5_tx_bclk" },

	{ .index = -1 },

	{ .fw_name = "mlb_clk" },

	{ .fw_name = "dummy" },



};
@@ -279,8 +279,10 @@ static int clk_imx_acm_attach_pm_domains(struct device *dev, 


	for (i = 0; i < dev_pm->num_domains; i++) {

		dev_pm->pd_dev[i] = dev_pm_domain_attach_by_id(dev, i);

		if (IS_ERR(dev_pm->pd_dev[i]))

			return PTR_ERR(dev_pm->pd_dev[i]);

		if (IS_ERR(dev_pm->pd_dev[i])) {

			ret = PTR_ERR(dev_pm->pd_dev[i]);

			goto detach_pm;

		}



		dev_pm->pd_dev_link[i] = device_link_add(dev,

							 dev_pm->pd_dev[i],
@@ -308,20 +310,18 @@ static int clk_imx_acm_attach_pm_domains(struct device *dev, 
 * @dev: deivice pointer

 * @dev_pm: multi power domain for device

 */

static int clk_imx_acm_detach_pm_domains(struct device *dev,

static void clk_imx_acm_detach_pm_domains(struct device *dev,

					  struct clk_imx_acm_pm_domains *dev_pm)

{

	int i;



	if (dev_pm->num_domains <= 1)

		return 0;

		return;



	for (i = 0; i < dev_pm->num_domains; i++) {

		device_link_del(dev_pm->pd_dev_link[i]);

		dev_pm_domain_detach(dev_pm->pd_dev[i], false);

	}



	return 0;

}



static int imx8_acm_clk_probe(struct platform_device *pdev)
@@ -371,22 +371,25 @@ static int imx8_acm_clk_probe(struct platform_device *pdev) 
										sels[i].shift, sels[i].width,

										0, NULL, NULL);

		if (IS_ERR(hws[sels[i].clkid])) {

			pm_runtime_disable(&pdev->dev);

			ret = PTR_ERR(hws[sels[i].clkid]);

			imx_check_clk_hws(hws, IMX_ADMA_ACM_CLK_END);

			goto err_clk_register;

		}

	}



	imx_check_clk_hws(hws, IMX_ADMA_ACM_CLK_END);



	ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_hw_data);

	if (ret < 0) {

		dev_err(dev, "failed to register hws for ACM\n");

		pm_runtime_disable(&pdev->dev);

		goto err_clk_register;

	}



err_clk_register:

	pm_runtime_put_sync(&pdev->dev);

	return 0;



err_clk_register:

	pm_runtime_put_sync(&pdev->dev);

	pm_runtime_disable(&pdev->dev);

	clk_imx_acm_detach_pm_domains(&pdev->dev, &priv->dev_pm);



	return ret;

}

drivers/clk/imx/clk-imx8dxl-rsrc.c

+1 −2
Original line number Diff line number Diff line
@@ -47,11 +47,10 @@ static u32 imx8dxl_clk_scu_rsrc_table[] = { 
	IMX_SC_R_SDHC_2,

	IMX_SC_R_ENET_0,

	IMX_SC_R_ENET_1,

	IMX_SC_R_MLB_0,

	IMX_SC_R_USB_1,

	IMX_SC_R_NAND,

	IMX_SC_R_M4_0_I2C,

	IMX_SC_R_M4_0_UART,

	IMX_SC_R_M4_0_I2C,

	IMX_SC_R_ELCDIF_PLL,

	IMX_SC_R_AUDIO_PLL_0,

	IMX_SC_R_AUDIO_PLL_1,

drivers/clk/imx/clk-imx8mq.c

+10 −7
Original line number Diff line number Diff line
@@ -288,8 +288,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) 
	void __iomem *base;

	int err;



	clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,

					  IMX8MQ_CLK_END), GFP_KERNEL);

	clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, IMX8MQ_CLK_END), GFP_KERNEL);

	if (WARN_ON(!clk_hw_data))

		return -ENOMEM;
@@ -306,10 +305,12 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) 
	hws[IMX8MQ_CLK_EXT4] = imx_get_clk_hw_by_name(np, "clk_ext4");



	np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-anatop");

	base = of_iomap(np, 0);

	base = devm_of_iomap(dev, np, 0, NULL);

	of_node_put(np);

	if (WARN_ON(!base))

		return -ENOMEM;

	if (WARN_ON(IS_ERR(base))) {

		err = PTR_ERR(base);

		goto unregister_hws;

	}



	hws[IMX8MQ_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x28, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));

	hws[IMX8MQ_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x18, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
@@ -395,8 +396,10 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) 


	np = dev->of_node;

	base = devm_platform_ioremap_resource(pdev, 0);

	if (WARN_ON(IS_ERR(base)))

		return PTR_ERR(base);

	if (WARN_ON(IS_ERR(base))) {

		err = PTR_ERR(base);

		goto unregister_hws;

	}



	/* CORE */

	hws[IMX8MQ_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mq_a53_sels, base + 0x8000);