Commit 70839da6 authored by Aurabindo Pillai's avatar Aurabindo Pillai Committed by Alex Deucher
Browse files

drm/amd/display: Add new DCN401 sources 



Add initial support for DCN 4.0.1.

Signed-off-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: default avatarRodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 59a0c03a

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dalsmc.h

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// SPDX-License-Identifier: MIT

//

// Copyright 2024 Advanced Micro Devices, Inc.



#ifndef DALSMC_H

#define DALSMC_H



#define DALSMC_VERSION 0x1



// SMU Response Codes:

#define DALSMC_Result_OK                   0x1

#define DALSMC_Result_Failed               0xFF

#define DALSMC_Result_UnknownCmd           0xFE

#define DALSMC_Result_CmdRejectedPrereq    0xFD

#define DALSMC_Result_CmdRejectedBusy      0xFC







// Message Definitions:

#define DALSMC_MSG_TestMessage                    0x1

#define DALSMC_MSG_GetSmuVersion                  0x2

#define DALSMC_MSG_GetDriverIfVersion             0x3

#define DALSMC_MSG_GetMsgHeaderVersion            0x4

#define DALSMC_MSG_SetDalDramAddrHigh             0x5

#define DALSMC_MSG_SetDalDramAddrLow              0x6

#define DALSMC_MSG_TransferTableSmu2Dram          0x7

#define DALSMC_MSG_TransferTableDram2Smu          0x8

#define DALSMC_MSG_SetHardMinByFreq               0x9

#define DALSMC_MSG_SetHardMaxByFreq               0xA

#define DALSMC_MSG_GetDpmFreqByIndex              0xB

#define DALSMC_MSG_GetDcModeMaxDpmFreq            0xC

#define DALSMC_MSG_SetMinDeepSleepDcfclk          0xD

#define DALSMC_MSG_NumOfDisplays                  0xE

#define DALSMC_MSG_SetExternalClientDfCstateAllow 0xF

#define DALSMC_MSG_BacoAudioD3PME                 0x10

#define DALSMC_MSG_SetFclkSwitchAllow             0x11

#define DALSMC_MSG_SetCabForUclkPstate            0x12

#define DALSMC_MSG_SetWorstCaseUclkLatency        0x13

#define DALSMC_Message_Count                      0x14



typedef enum {

  FCLK_SWITCH_DISALLOW,

  FCLK_SWITCH_ALLOW,

} FclkSwitchAllow_e;



#endif

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

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File added.

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drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h

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// SPDX-License-Identifier: MIT

//

// Copyright 2024 Advanced Micro Devices, Inc.



#ifndef __DCN401_CLK_MGR_H_

#define __DCN401_CLK_MGR_H_



void dcn401_init_clocks(struct clk_mgr *clk_mgr_base);



void dcn401_clk_mgr_construct(struct dc_context *ctx,

		struct clk_mgr_internal *clk_mgr,

		struct pp_smu_funcs *pp_smu,

		struct dccg *dccg);



void dcn401_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,

		struct dc_state *context, bool safe_to_lower, int dppclk_khz);



void dcn401_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr);







#endif /* __DCN401_CLK_MGR_H_ */

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

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// SPDX-License-Identifier: MIT

//

// Copyright 2024 Advanced Micro Devices, Inc.



#include "dcn401_clk_mgr_smu_msg.h"



#include "clk_mgr_internal.h"

#include "reg_helper.h"



#include "dalsmc.h"

#include "dcn401_smu14_driver_if.h"



#define mmDAL_MSG_REG  0x1628A

#define mmDAL_ARG_REG  0x16273

#define mmDAL_RESP_REG 0x16274



#define REG(reg_name) \

	mm ## reg_name



#include "logger_types.h"



#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }



/*

 * Function to be used instead of REG_WAIT macro because the wait ends when

 * the register is NOT EQUAL to zero, and because the translation in msg_if.h

 * won't work with REG_WAIT.

 */

static uint32_t dcn401_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)

{

	uint32_t reg = 0;



	do {

		reg = REG_READ(DAL_RESP_REG);

		if (reg)

			break;



		if (delay_us >= 1000)

			msleep(delay_us/1000);

		else if (delay_us > 0)

			udelay(delay_us);

	} while (max_retries--);



	return reg;

}



static bool dcn401_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32_t param_in, uint32_t *param_out)

{

	/* Wait for response register to be ready */

	dcn401_smu_wait_for_response(clk_mgr, 10, 200000);



	/* Clear response register */

	REG_WRITE(DAL_RESP_REG, 0);



	/* Set the parameter register for the SMU message */

	REG_WRITE(DAL_ARG_REG, param_in);



	/* Trigger the message transaction by writing the message ID */

	REG_WRITE(DAL_MSG_REG, msg_id);



	/* Wait for response */

	if (dcn401_smu_wait_for_response(clk_mgr, 10, 200000) == DALSMC_Result_OK) {

		if (param_out)

			*param_out = REG_READ(DAL_ARG_REG);



		return true;

	}



	return false;

}



void dcn401_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool enable)

{

	smu_print("FCLK P-state support value is : %d\n", enable);



	dcn401_smu_send_msg_with_param(clk_mgr,

			DALSMC_MSG_SetFclkSwitchAllow, enable ? FCLK_PSTATE_SUPPORTED : FCLK_PSTATE_NOTSUPPORTED, NULL);

}



void dcn401_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways)

{

	uint32_t param = (num_ways << 1) | (num_ways > 0);



	dcn401_smu_send_msg_with_param(clk_mgr, DALSMC_MSG_SetCabForUclkPstate, param, NULL);

	smu_print("Numways for SubVP : %d\n", num_ways);

}



void dcn401_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)

{

	smu_print("SMU Transfer WM table DRAM 2 SMU\n");



	dcn401_smu_send_msg_with_param(clk_mgr,

			DALSMC_MSG_TransferTableDram2Smu, TABLE_WATERMARKS, NULL);

}



void dcn401_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr)

{

	smu_print("SMU Set PME workaround\n");



	dcn401_smu_send_msg_with_param(clk_mgr,

		DALSMC_MSG_BacoAudioD3PME, 0, NULL);

}



/* Returns the actual frequency that was set in MHz, 0 on failure */

unsigned int dcn401_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz)

{

	uint32_t response = 0;



	/* bits 23:16 for clock type, lower 16 bits for frequency in MHz */

	uint32_t param = (clk << 16) | freq_mhz;



	smu_print("SMU Set hard min by freq: clk = %d, freq_mhz = %d MHz\n", clk, freq_mhz);



	dcn401_smu_send_msg_with_param(clk_mgr,

			DALSMC_MSG_SetHardMinByFreq, param, &response);



	smu_print("SMU Frequency set = %d KHz\n", response);



	return response;

}

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

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// SPDX-License-Identifier: MIT

//

// Copyright 2024 Advanced Micro Devices, Inc.



#ifndef __DCN401_CLK_MGR_SMU_MSG_H_

#define __DCN401_CLK_MGR_SMU_MSG_H_



#include "os_types.h"

#include "core_types.h"

#include "dcn32/dcn32_clk_mgr_smu_msg.h"



#define FCLK_PSTATE_NOTSUPPORTED       0x00

#define FCLK_PSTATE_SUPPORTED          0x01



void dcn401_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool enable);

void dcn401_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways);

void dcn401_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);

void dcn401_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr);

unsigned int dcn401_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz);



#endif /* __DCN401_CLK_MGR_SMU_MSG_H_ */