Commit 7083e142 authored by Ryan Chen's avatar Ryan Chen Committed by Thomas Gleixner
Browse files

dt-bindings: interrupt-controller: aspeed,ast2700: Correct #interrupt-cells and interrupts count 



Update the AST2700 interrupt controller binding to match the actual
hardware and the irq-aspeed-intc driver behavior.

 - Interrupts:

    First-level INTC banks request multiple interrupt lines to the root
    GIC, with a maximum of 10 per bank. Second-level INTC banks request
    only one interrupt line to their parent INTC-IC. Therefore, set the
    interrupts property to allow a minimum of 1 and a maximum of 10
    entries.

 - #interrupt-cells:

    Set '#interrupt-cells' to <1> since the aspeed intc driver does not
    support specifying a trigger type; only the interrupt index is used.

Signed-off-by: default avatarRyan Chen <ryan_chen@aspeedtech.com>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Acked-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://patch.msgid.link/20251030060155.2342604-2-ryan_chen@aspeedtech.com
parent 47a4ebbf

Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml

+9 −4
Original line number Diff line number Diff line
@@ -25,13 +25,14 @@ properties: 
  interrupt-controller: true



  '#interrupt-cells':

    const: 2

    const: 1

    description:

      The first cell is the IRQ number, the second cell is the trigger

      type as defined in interrupt.txt in this directory.



  interrupts:

    maxItems: 6

    minItems: 1

    maxItems: 10

    description: |

      Depend to which INTC0 or INTC1 used.

      INTC0 and INTC1 are two kinds of interrupt controller with enable and raw
@@ -74,13 +75,17 @@ examples: 
        interrupt-controller@12101b00 {

            compatible = "aspeed,ast2700-intc-ic";

            reg = <0 0x12101b00 0 0x10>;

            #interrupt-cells = <2>;

            #interrupt-cells = <1>;

            interrupt-controller;

            interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;

                         <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;

        };

    };