Unverified Commit 7105fdd5 authored by Rob Herring (Arm)'s avatar Rob Herring (Arm) Committed by Mark Brown
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spi: dt-bindings: Convert marvell,orion-spi to DT schema 



Convert the Marvell Orion SPI binding to schema.

Update compatible strings to what is in use. Generally,
"marvell,orion-spi" is a fallback compatible, but newer variants only
use "marvell,armada-380-spi".

Mark cell-index as deprecated and not required as some instances don't
use it already.

Signed-off-by: default avatarRob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20250702222643.2761617-1-robh@kernel.org


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent d2c0e955

Documentation/devicetree/bindings/spi/marvell,orion-spi.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/spi/marvell,orion-spi.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Marvell Orion SPI controller



maintainers:

  - Andrew Lunn <andrew@lunn.ch>

  - Gregory CLEMENT <gregory.clement@bootlin.com>



allOf:

  - $ref: /schemas/spi/spi-controller.yaml#



properties:

  compatible:

    oneOf:

      - enum:

          - marvell,orion-spi

          - marvell,armada-380-spi  # For ap80x and cp11x

      - items:

          - enum:

              - marvell,armada-370-spi

              - marvell,armada-375-spi

              - marvell,armada-380-spi

              - marvell,armada-390-spi

              - marvell,armada-xp-spi

          - const: marvell,orion-spi



  cell-index:

    description: Instance id for the SPI controller

    deprecated: true



  reg:

    minItems: 1

    items:

      - description: control registers

      - description: CS0 MBUS target/attribute registers for direct mode

      - description: CS1 MBUS target/attribute registers for direct mode

      - description: CS2 MBUS target/attribute registers for direct mode

      - description: CS3 MBUS target/attribute registers for direct mode

      - description: CS4 MBUS target/attribute registers for direct mode

      - description: CS5 MBUS target/attribute registers for direct mode

      - description: CS6 MBUS target/attribute registers for direct mode

      - description: CS7 MBUS target/attribute registers for direct mode



  clocks:

    minItems: 1

    maxItems: 2



  clock-names:

    items:

      - const: core

      - const: axi



  interrupts:

    maxItems: 1



required:

  - compatible

  - reg

  - clocks



unevaluatedProperties: false



examples:

  - |

    spi@10600 {

      compatible = "marvell,orion-spi";

      #address-cells = <1>;

      #size-cells = <0>;

      cell-index = <0>;

      reg = <0x10600 0x28>;

      clocks = <&coreclk 0>;

      interrupts = <23>;

    };

  - |

    #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))



    bus {

        #address-cells = <2>;

        #size-cells = <1>;



        spi@10600 {

          compatible = "marvell,orion-spi";

          #address-cells = <1>;

          #size-cells = <0>;

          cell-index = <0>;

          reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x28>, /* control */

                <MBUS_ID(0x01, 0x1e) 0 0xffffffff>, /* CS0 */

                <MBUS_ID(0x01, 0x5e) 0 0xffffffff>, /* CS1 */

                <MBUS_ID(0x01, 0x9e) 0 0xffffffff>, /* CS2 */

                <MBUS_ID(0x01, 0xde) 0 0xffffffff>, /* CS3 */

                <MBUS_ID(0x01, 0x1f) 0 0xffffffff>, /* CS4 */

                <MBUS_ID(0x01, 0x5f) 0 0xffffffff>, /* CS5 */

                <MBUS_ID(0x01, 0x9f) 0 0xffffffff>, /* CS6 */

                <MBUS_ID(0x01, 0xdf) 0 0xffffffff>; /* CS7 */

          clocks = <&coreclk 0>;

          interrupts = <23>;

        };

    };

Documentation/devicetree/bindings/spi/spi-orion.txt

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Marvell Orion SPI device



Required properties:

- compatible : should be on of the following:

    - "marvell,orion-spi" for the Orion, mv78x00, Kirkwood and Dove SoCs

    - "marvell,armada-370-spi", for the Armada 370 SoCs

    - "marvell,armada-375-spi", for the Armada 375 SoCs

    - "marvell,armada-380-spi", for the Armada 38x SoCs

    - "marvell,armada-390-spi", for the Armada 39x SoCs

    - "marvell,armada-xp-spi", for the Armada XP SoCs

- reg : offset and length of the register set for the device.

	This property can optionally have additional entries to configure

	the SPI direct access mode that some of the Marvell SoCs support

	additionally to the normal indirect access (PIO) mode. The values

	for the MBus "target" and "attribute" are defined in the Marvell

	SoC "Functional Specifications" Manual in the chapter "Marvell

	Core Processor Address Decoding".

	The eight register sets following the control registers refer to

	chip-select lines 0 through 7 respectively.

- cell-index : Which of multiple SPI controllers is this.

- clocks : pointers to the reference clocks for this device, the first

	   one is the one used for the clock on the spi bus, the

	   second one is optional and is the clock used for the

	   functional part of the controller



Optional properties:

- interrupts : Is currently not used.

- clock-names : names of used clocks, mandatory if the second clock is

		used, the name must be "core", and "axi" (the latter

		is only for Armada 7K/8K).





Example:

       spi@10600 {

	       compatible = "marvell,orion-spi";

	       #address-cells = <1>;

	       #size-cells = <0>;

	       cell-index = <0>;

	       reg = <0x10600 0x28>;

	       interrupts = <23>;

       };



Example with SPI direct mode support (optionally):

	spi0: spi@10600 {

		compatible = "marvell,orion-spi";

		#address-cells = <1>;

		#size-cells = <0>;

		cell-index = <0>;

		reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x28>, /* control */

		      <MBUS_ID(0x01, 0x1e) 0 0xffffffff>, /* CS0 */

		      <MBUS_ID(0x01, 0x5e) 0 0xffffffff>, /* CS1 */

		      <MBUS_ID(0x01, 0x9e) 0 0xffffffff>, /* CS2 */

		      <MBUS_ID(0x01, 0xde) 0 0xffffffff>, /* CS3 */

		      <MBUS_ID(0x01, 0x1f) 0 0xffffffff>, /* CS4 */

		      <MBUS_ID(0x01, 0x5f) 0 0xffffffff>, /* CS5 */

		      <MBUS_ID(0x01, 0x9f) 0 0xffffffff>, /* CS6 */

		      <MBUS_ID(0x01, 0xdf) 0 0xffffffff>; /* CS7 */

		interrupts = <23>;

	};



To enable the direct mode, the board specific 'ranges' property in the

'soc' node needs to add the entries for the desired SPI controllers

and its chip-selects that are used in the direct mode instead of PIO

mode. Here an example for this (SPI controller 0, device 1 and SPI

controller 1, device 2 are used in direct mode. All other SPI device

are used in the default indirect (PIO) mode):

	soc {

		/*

		 * Enable the SPI direct access by configuring an entry

		 * here in the board-specific ranges property

		 */

		ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000>,	/* internal regs */

			 <MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>,	/* BootROM       */

			 <MBUS_ID(0x01, 0x5e) 0 0 0xf1100000 0x10000>,	/* SPI0-DEV1 */

			 <MBUS_ID(0x01, 0x9a) 0 0 0xf1110000 0x10000>;	/* SPI1-DEV2 */



For further information on the MBus bindings, please see the MBus

DT documentation:

Documentation/devicetree/bindings/bus/mvebu-mbus.txt