Commit 7137cf75 authored by Jinrong Liang's avatar Jinrong Liang Committed by Sean Christopherson
Browse files

KVM: selftests: Test consistency of CPUID with num of gp counters 



Add a test to verify that KVM correctly emulates MSR-based accesses to
general purpose counters based on guest CPUID, e.g. that accesses to
non-existent counters #GP and accesses to existent counters succeed.

Note, for compatibility reasons, KVM does not emulate #GP when
MSR_P6_PERFCTR[0|1] is not present (writes should be dropped).

Co-developed-by: default avatarLike Xu <likexu@tencent.com>
Signed-off-by: default avatarLike Xu <likexu@tencent.com>
Signed-off-by: default avatarJinrong Liang <cloudliang@tencent.com>
Co-developed-by: default avatarSean Christopherson <seanjc@google.com>
Tested-by: default avatarDapeng Mi <dapeng1.mi@linux.intel.com>
Link: https://lore.kernel.org/r/20240109230250.424295-19-seanjc@google.com


Signed-off-by: default avatarSean Christopherson <seanjc@google.com>
parent 3e26b825

tools/testing/selftests/kvm/x86_64/pmu_counters_test.c

+99 −0
Original line number Diff line number Diff line
@@ -270,9 +270,103 @@ static void test_arch_events(uint8_t pmu_version, uint64_t perf_capabilities, 
	kvm_vm_free(vm);

}



/*

 * Limit testing to MSRs that are actually defined by Intel (in the SDM).  MSRs

 * that aren't defined counter MSRs *probably* don't exist, but there's no

 * guarantee that currently undefined MSR indices won't be used for something

 * other than PMCs in the future.

 */

#define MAX_NR_GP_COUNTERS	8

#define MAX_NR_FIXED_COUNTERS	3



#define GUEST_ASSERT_PMC_MSR_ACCESS(insn, msr, expect_gp, vector)		\

__GUEST_ASSERT(expect_gp ? vector == GP_VECTOR : !vector,			\

	       "Expected %s on " #insn "(0x%x), got vector %u",			\

	       expect_gp ? "#GP" : "no fault", msr, vector)			\



#define GUEST_ASSERT_PMC_VALUE(insn, msr, val, expected)			\

	__GUEST_ASSERT(val == expected_val,					\

		       "Expected " #insn "(0x%x) to yield 0x%lx, got 0x%lx",	\

		       msr, expected_val, val);



static void guest_rd_wr_counters(uint32_t base_msr, uint8_t nr_possible_counters,

				 uint8_t nr_counters)

{

	uint8_t i;



	for (i = 0; i < nr_possible_counters; i++) {

		/*

		 * TODO: Test a value that validates full-width writes and the

		 * width of the counters.

		 */

		const uint64_t test_val = 0xffff;

		const uint32_t msr = base_msr + i;

		const bool expect_success = i < nr_counters;



		/*

		 * KVM drops writes to MSR_P6_PERFCTR[0|1] if the counters are

		 * unsupported, i.e. doesn't #GP and reads back '0'.

		 */

		const uint64_t expected_val = expect_success ? test_val : 0;

		const bool expect_gp = !expect_success && msr != MSR_P6_PERFCTR0 &&

				       msr != MSR_P6_PERFCTR1;

		uint8_t vector;

		uint64_t val;



		vector = wrmsr_safe(msr, test_val);

		GUEST_ASSERT_PMC_MSR_ACCESS(WRMSR, msr, expect_gp, vector);



		vector = rdmsr_safe(msr, &val);

		GUEST_ASSERT_PMC_MSR_ACCESS(RDMSR, msr, expect_gp, vector);



		/* On #GP, the result of RDMSR is undefined. */

		if (!expect_gp)

			GUEST_ASSERT_PMC_VALUE(RDMSR, msr, val, expected_val);



		vector = wrmsr_safe(msr, 0);

		GUEST_ASSERT_PMC_MSR_ACCESS(WRMSR, msr, expect_gp, vector);

	}

	GUEST_DONE();

}



static void guest_test_gp_counters(void)

{

	uint8_t nr_gp_counters = 0;

	uint32_t base_msr;



	if (guest_get_pmu_version())

		nr_gp_counters = this_cpu_property(X86_PROPERTY_PMU_NR_GP_COUNTERS);



	if (this_cpu_has(X86_FEATURE_PDCM) &&

	    rdmsr(MSR_IA32_PERF_CAPABILITIES) & PMU_CAP_FW_WRITES)

		base_msr = MSR_IA32_PMC0;

	else

		base_msr = MSR_IA32_PERFCTR0;



	guest_rd_wr_counters(base_msr, MAX_NR_GP_COUNTERS, nr_gp_counters);

}



static void test_gp_counters(uint8_t pmu_version, uint64_t perf_capabilities,

			     uint8_t nr_gp_counters)

{

	struct kvm_vcpu *vcpu;

	struct kvm_vm *vm;



	vm = pmu_vm_create_with_one_vcpu(&vcpu, guest_test_gp_counters,

					 pmu_version, perf_capabilities);



	vcpu_set_cpuid_property(vcpu, X86_PROPERTY_PMU_NR_GP_COUNTERS,

				nr_gp_counters);



	run_vcpu(vcpu);



	kvm_vm_free(vm);

}



static void test_intel_counters(void)

{

	uint8_t nr_arch_events = kvm_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH);

	uint8_t nr_gp_counters = kvm_cpu_property(X86_PROPERTY_PMU_NR_GP_COUNTERS);

	uint8_t pmu_version = kvm_cpu_property(X86_PROPERTY_PMU_VERSION);

	unsigned int i;

	uint8_t v, j;
@@ -336,6 +430,11 @@ static void test_intel_counters(void) 
				for (k = 0; k < nr_arch_events; k++)

					test_arch_events(v, perf_caps[i], j, BIT(k));

			}



			pr_info("Testing GP counters, PMU version %u, perf_caps = %lx\n",

				v, perf_caps[i]);

			for (j = 0; j <= nr_gp_counters; j++)

				test_gp_counters(v, perf_caps[i], j);

		}

	}

}